公开(公告)号：US09831118B1

公开(公告)日：2017-11-28

申请号：US15163236

申请日：2016-05-24

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Yingda Dong ,  Jayavel Pachamuthu ,  Ching-Huang Lu

IPC: H01L21/768 ,  H01L27/115 ,  H01L23/532 ,  H01L21/28 ,  H01L23/528 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L21/7682 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833

Abstract: Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates.

公开(公告)号：US09779948B1

公开(公告)日：2017-10-03

申请号：US15185866

申请日：2016-06-17

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Yanli Zhang ,  Ching-Huang Lu ,  Zhenyu Lu

IPC: H01L21/28 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/28282 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Disclosed herein are methods of fabricating a source side select (SGS) transistor in 3D memory. The threshold voltage of the SGS transistor accurately meets a target threshold voltage. The SGS transistor has a semiconductor body that resides in a memory hole formed in a stack of alternating layers of two materials. During fabrication, a sacrificial layer may be removed to create recesses between dielectric layers in a stack. The sacrificial layer may be removed by introducing an etchant into slits formed in the stack. Thus, the recess may expose sidewalls of the body of the SGS transistor. An impurity may be introduced into this recess, by way of a slit, in order to dope the source side select transistor. This allows for precise control over the doping profile, which in turn provides for precise control over the threshold voltage of the SGS transistor.

公开(公告)号：US09761320B1

公开(公告)日：2017-09-12

申请号：US15383852

申请日：2016-12-19

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Ching-Huang Lu ,  Wei Zhao

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during the last phase of a sensing operation when all voltage signals are ramped down to a steady state voltage. In one aspect, the voltages of the source side word line, WL0, and an adjacent dummy word line, WLDS1, are ramped down after the voltages of remaining word lines are ramped down. This can occur regardless of whether WL0 is the selected word line which is programmed or read. The technique can be applied after the sensing which occurs in a read or program-verify operation. Another option involves elevating the voltage of the selected word line so that all word lines are ramped down from the same level, such as a read pass level. The techniques are particularly useful when the memory device includes an interface in the channel between epitaxial silicon and polysilicon.

公开(公告)号：US20210082515A1

公开(公告)日：2021-03-18

申请号：US17102712

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/1157

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

公开(公告)号：US10943917B2

公开(公告)日：2021-03-09

申请号：US16388054

申请日：2019-04-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Makoto Koto ,  Sayako Nagamine ,  Ching-Huang Lu ,  Wei Zhao ,  Yanli Zhang ,  James Kai

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L21/762 ,  H01L27/11565 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

公开(公告)号：US20200312410A1

公开(公告)日：2020-10-01

申请号：US16898145

申请日：2020-06-10

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep ,  Zhengyi Zhang

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/04

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

公开(公告)号：US20200265897A1

公开(公告)日：2020-08-20

申请号：US16280297

申请日：2019-02-20

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11578 ,  H01L27/1157

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

公开(公告)号：US10706941B1

公开(公告)日：2020-07-07

申请号：US16371289

申请日：2019-04-01

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep ,  Zhengyi Zhang

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

公开(公告)号：US10276248B1

公开(公告)日：2019-04-30

申请号：US15849019

申请日：2017-12-20

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34

Abstract: Techniques for reducing a downshift in the threshold voltage of a select gate transistor of a memory device. Due to an electric field in a NAND string, holes can move in a charge-trapping layer from a dummy memory cell to a select gate transistor and combine with electrons in the transistor, reducing the threshold voltage. In one approach, the electric field is reduced at the end of a sensing operation by ramping down the voltage of the dummy memory cells before ramping down the voltage of the select gate transistors. The ramp down of the voltage of the selected memory cells can occur after ramping down the voltage of the dummy memory cells and before ramping down of the voltage of the select gate transistors. A further option involves elevating the voltage of the select gate transistors before it is ramped down.

公开(公告)号：US10249372B2

公开(公告)日：2019-04-02

申请号：US15694008

申请日：2017-09-01

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.