公开(公告)号：US10249679B2

公开(公告)日：2019-04-02

申请号：US14979282

申请日：2015-12-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L27/16 ,  H01L35/02 ,  H01L23/38 ,  H01L35/34

Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.

公开(公告)号：US20180158530A1

公开(公告)日：2018-06-07

申请号：US15886243

申请日：2018-02-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: G11C16/22 ,  H01L21/311 ,  H01L27/115 ,  H01L23/00 ,  H01L29/78 ,  H01L21/66 ,  H01L21/8238 ,  H01L21/74 ,  H01L21/8234

CPC classification number: G11C16/22 ,  G06F21/87 ,  H01L21/31116 ,  H01L21/74 ,  H01L21/823481 ,  H01L21/823892 ,  H01L22/14 ,  H01L22/34 ,  H01L23/57 ,  H01L23/576 ,  H01L27/115 ,  H01L29/7846

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

公开(公告)号：US20180145039A1

公开(公告)日：2018-05-24

申请号：US15596772

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L23/28 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L23/57 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/28 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/573

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.

公开(公告)号：US09978847B2

公开(公告)日：2018-05-22

申请号：US15454184

申请日：2017-03-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/08

CPC classification number: H01L29/4236 ,  H01L21/02236 ,  H01L21/28167 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

公开(公告)号：US09875870B2

公开(公告)日：2018-01-23

申请号：US15477876

申请日：2017-04-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Sebastian Orellana

IPC: H01H49/00 ,  H01H59/00

CPC classification number: H01H49/00 ,  H01H59/0009 ,  H01H2001/0052 ,  H01H2001/0057 ,  H01H2001/0078 ,  H01H2061/006 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.

公开(公告)号：US09812399B2

公开(公告)日：2017-11-07

申请号：US15137063

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Jean-Philippe Escales

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228

Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.

公开(公告)号：US20170194267A1

公开(公告)日：2017-07-06

申请号：US15466396

申请日：2017-03-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Guilhem Bouton

IPC: H01L23/00 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L23/576 ,  G06F17/5068 ,  H01L21/768 ,  H01L21/76838 ,  H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

公开(公告)号：US20160093696A1

公开(公告)日：2016-03-31

申请号：US14953692

申请日：2015-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L21/763 ,  H01L27/112 ,  H01L21/762

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20160064339A1

公开(公告)日：2016-03-03

申请号：US14829292

申请日：2015-08-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Guilhem Bouton

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L23/576 ,  G06F17/5068 ,  H01L21/768 ,  H01L21/76838 ,  H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

Abstract translation: 集成电路包括其上形成有多个功能块的基板。 至少两个相同的功能块分别设置在集成电路上的两个或更多个不同位置处。 提供了在功能块的附近和/或内部的电活动的虚拟模块，其中至少两个不同的电不活动的虚拟模块包括在相应的邻域和/或至少两个相同功能块的内部。

公开(公告)号：US09263518B2

公开(公告)日：2016-02-16

申请号：US14300663

申请日：2014-06-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L23/522

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66568 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.

Abstract translation: 集成电路包括衬底和至少一个NMOS晶体管，其在衬底中具有由绝缘区域包围的有源区域。 绝缘区域形成为包括至少一个区域，其中绝缘区域具有通过由基板的一部分形成的分离区域彼此分离的两个绝缘区域。