公开(公告)号：US20240296253A1

公开(公告)日：2024-09-05

申请号：US18661060

申请日：2024-05-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G06F21/75 ,  G06F21/72 ,  G11C11/4096 ,  H01L27/088 ,  H03K19/17768

CPC classification number: G06F21/75 ,  G06F21/72 ,  G11C11/4096 ,  H01L27/0883 ,  H03K19/17768

Abstract: An embodiment system comprises a physical unclonable function device, wherein the device comprises a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution, and a processing circuit configured to deliver, to an output interface of the device, a group of output data based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly.

公开(公告)号：US12057180B2

公开(公告)日：2024-08-06

申请号：US17934102

申请日：2022-09-21

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Antonino Conte ,  Francois Maugain

IPC: G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  H10B41/30 ,  H10B41/40

CPC classification number: G11C16/3445 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/349 ,  H10B41/30 ,  H10B41/40

Abstract: In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.

公开(公告)号：US20230282286A1

公开(公告)日：2023-09-07

申请号：US18173472

申请日：2023-02-23

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Marco Bildgen

IPC: G11C16/22 ,  G11C16/16 ,  G06F21/78

CPC classification number: G11C16/22 ,  G11C16/16 ,  G06F21/78 ,  H10B41/30

Abstract: An integrated circuit comprises a memory device including a memory plane having non-volatile memory cells and being non-observable in read mode from outside the memory device, a controller, internal to the memory device, configured to detect the memorized content of the memory plane, and when the memorized content contains locking content, automatically lock any access to the memory plane from outside the memory device, the integrated circuit then being in a locked status, and authorize delivery outside the memory device of at least one sensitive datum stored in the memory plane.

公开(公告)号：US20230162764A1

公开(公告)日：2023-05-25

申请号：US17902171

申请日：2022-09-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Thierry Giovinazzi

IPC: G11C7/10 ,  G11C7/22 ,  H03K5/135 ,  H03K5/1534

CPC classification number: G11C7/1066 ,  G11C7/222 ,  H03K5/135 ,  H03K5/1534

Abstract: The present description concerns an electronic device including: a first input configured to receive a clock signal, coupled by a first input buffer to a first circuit; and at least an output coupled by an output buffer to the first circuit, the output buffer being synchronized on first edges of the clock signal, wherein the first input buffer includes a data input coupled to the first input and is configured to maintain the value on its output constant whatever the value on its data input during a duration following each first edge of the clock signal.

公开(公告)号：US10796763B2

公开(公告)日：2020-10-06

申请号：US16256525

申请日：2019-01-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Francesco La Rosa ,  Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/08 ,  G11C16/32 ,  G11C16/30 ,  G11C16/10

Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.

公开(公告)号：US10560089B2

公开(公告)日：2020-02-11

申请号：US16161531

申请日：2018-10-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Borrel ,  Jimmy Fort ,  Francesco La Rosa

IPC: H03L5/02 ,  H03K17/20 ,  H03K17/22

Abstract: A power supply voltage is monitored by a monitoring circuit including a band gap voltage generator core including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the band gap voltage generator core generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.

公开(公告)号：US10403730B2

公开(公告)日：2019-09-03

申请号：US15914846

申请日：2018-03-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Julien Delalleau

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11521 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11524 ,  H01L29/78 ,  G11C16/04 ,  H01L21/306

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US10281512B2

公开(公告)日：2019-05-07

申请号：US15387370

申请日：2016-12-21

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G01R31/02 ,  G01R31/28 ,  G04F10/10

Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.

公开(公告)号：US20190067309A1

公开(公告)日：2019-02-28

申请号：US16175030

申请日：2018-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/11531 ,  H01L29/861 ,  G11C16/04 ,  H01L29/739 ,  H01L29/66 ,  H01L29/788 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L29/16 ,  H01L27/11526 ,  H01L27/11521 ,  H01L27/08 ,  H01L27/11536 ,  H01L27/12 ,  H01L27/06 ,  H01L29/36

Abstract: An integrated circuit includes an insulating layer overlying a semiconductor substrate. A semiconductor layer of a first conductivity type overlies the insulating layer. A plurality of projecting regions that are spaced apart from each other overly the semiconductor layer. A sequence of PN junctions are in the semiconductor layer. Each PN junction is located at an edge of an associated projecting region. Each PN junction also extends vertically from an upper surface of the semiconductor layer to the insulating layer.

公开(公告)号：US10218336B2

公开(公告)日：2019-02-26

申请号：US15436817

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: H03L7/099 ,  H03L5/00 ,  G05F3/26 ,  H03K3/03 ,  H03K3/011 ,  G11C7/06 ,  H03L1/00

Abstract: A device and method can be used to manage the operation of a ring oscillator circuit. A master oscillator circuit generates a master supply voltage. The master supply voltage associated with a stable oscillation rate of the master oscillator circuit. The master oscillator circuit is supplied with current and is structurally identical to the ring oscillator circuit. A capacitive circuit is loaded with a load voltage originating from the master supply voltage. In response to a control signal, the ring oscillator circuit is supplied with a current controlled by a voltage delivered by the capacitive circuit, in such a way as to provide a stable oscillation rate for the ring oscillator circuit.