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    Non-volatile memory with double capa implant
    21.
    发明授权
    Non-volatile memory with double capa implant 有权

    公开(公告)号：US11031082B2

    公开(公告)日：2021-06-08

    申请号：US16866955

    申请日：2020-05-05

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet ,  Roberto Simola

    IPC: G11C16/04 ,  H01L27/11517 ,  H01L29/423

    Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

    Communication on an I2C bus
    24.
    发明授权
    Communication on an I2C bus 有权

    公开(公告)号：US09753886B2

    公开(公告)日：2017-09-05

    申请号：US14452620

    申请日：2014-08-06

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G06F13/00 ,  G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4282 ,  G06F13/4068 ,  G06F13/4291 ,  G06F2213/0016

    Abstract: A communication system includes an I2C bus interconnecting at least one first device and one second device. At least one direct data link, other than the I2C bus, interconnects the first and second devices. The system is configurable to operate in: a first operating mode providing for data only transmission between the first and second devices over the I2C bus; and a second operating mode providing for simultaneous data transmission between the first and second devices over both the I2C bus and said data link.

    Method for managing the operation of a circuit connected to a two-wire bus
    25.
    发明授权
    Method for managing the operation of a circuit connected to a two-wire bus 有权
    用于管理连接到二线总线的电路的操作的方法

    公开(公告)号：US09489334B2

    公开(公告)日：2016-11-08

    申请号：US14042344

    申请日：2013-09-30

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4282 ,  G06F13/4077

    Abstract: A method is provided for managing the operation of a circuit operating in a slave mode. The circuit is connected to a bus having at least two of wires and a priority logic level. The slave circuit imposes the priority logic level on a first wire of the bus. While imposing, the slave circuit detects a possible conflict on the first wire resulting from a forcing, external to the slave circuit, of the first wire to another logic level. Upon detecting a conflict, the slave circuit is placed in a state stopping the sending by the circuit of any data over the bus while leaving the circuit listening to the bus.

    Abstract translation: 提供了一种用于管理在从模式下操作的电路的操作的方法。 电路连接到具有至少两根导线和优先级逻辑电平的总线。 从电路在总线的第一根线上施加优先级逻辑电平。 在施加时，从电路检测到第一线上的强制（从属电路外部）将第一导线的第一导线的可能冲突与第一导线的另一逻辑电平相冲突。 在检测到冲突时，从电路处于停止通过总线发送任何数据的状态，同时让电路监听总线。

    Method for block-erasing a page-erasable EEPROM-type memory
    26.
    发明授权
    Method for block-erasing a page-erasable EEPROM-type memory 有权
    擦除可擦除EEPROM类型存储器的方法

    公开(公告)号：US09159430B2

    公开(公告)日：2015-10-13

    申请号：US14293860

    申请日：2014-06-02

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G11C16/14 ,  G11C16/04 ,  G11C16/16 ,  G11C16/30 ,  G11C11/56

    CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

    Abstract: A method for erasing a page-erasable EEPROM-type memory includes: the memory receiving a command associated with a set of addresses of pages of the memory to be erased, each page comprising several memory cell groups each forming a word, for each address of the set of addresses, selecting a word line corresponding to a page of the memory, and triggering the simultaneous erasing of all the selected word lines.

    Abstract translation: 擦除可擦除可擦除EEPROM型存储器的方法包括：存储器接收与要擦除的存储器的页面的一组地址相关联的命令，每个页面包括几个存储单元组，每个存储单元组形成一个单词，每个地址为 所述地址集合，选择与所述存储器的页面对应的字线，并且触发所有所选字线的同时擦除。

    Method for processing a non-volatile memory, in particular a memory of the EEPROM type, for the storage then the extraction of information, and corresponding memory device
    27.
    发明授权
    Method for processing a non-volatile memory, in particular a memory of the EEPROM type, for the storage then the extraction of information, and corresponding memory device 有权
    用于处理非易失性存储器的方法，特别是EEPROM类型的存储器，用于存储然后提取信息，以及相应的存储器件

    公开(公告)号：US09003265B2

    公开(公告)日：2015-04-07

    申请号：US13897940

    申请日：2013-05-20

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/1052

    Abstract: Method for processing a non-volatile memory designed to store words containing data bits and control bits allowing an error correction with an error correction code, the method comprising the storage of information in the memory plane comprising an operation for writing in the memory plane at least one digital word modified with respect to at least one initial digital word not having any erroneous bit, said at least one modified digital word containing a bit having a modified value with respect to the value of this bit in said at least one initial digital word, the other bits of the modified digital word having values identical to those of these same bits in the initial digital word, the position of the modified bit in said at least one modified digital word defining the value of the digital information.

    Abstract translation: 用于处理非易失性存储器的方法，所述非易失性存储器被设计为存储包含数据位的字和允许使用纠错码进行纠错的控制位，所述方法包括在所述存储器平面中存储信息，所述方法包括至少在所述存储器平面中写入的操作 关于至少一个不具有任何错误位的初始数字字修改的一个数字字，所述至少一个经修改的数字字包含相对于所述至少一个初始数字字中的该位的值具有修改值的位， 修改的数字字的其他位具有与初始数字字中的相同位相同的值，所述修改的位在所述至少一个修改的数字字中定义数字信息的值的位置。

    Low pass filter with an increased delay
    29.
    发明授权
    Low pass filter with an increased delay 有权
    低通滤波器延时增加

    公开(公告)号：US08884689B2

    公开(公告)日：2014-11-11

    申请号：US13868866

    申请日：2013-04-23

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet ,  Marc Battista

    IPC: H03B1/00 ,  H03K5/1252 ,  H03K5/13 ,  H03H11/04 ,  H03K5/00

    CPC classification number: H03H11/04 ,  H03K5/1252 ,  H03K5/13 ,  H03K2005/00156

    Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.

    Abstract translation: 低通滤波器包括被配置为接收第一逻辑信号的滤波器输入节点，被配置为提供第二逻辑信号的滤波器输出节点，包括耦合到输入节点的第一终端的电阻元件和耦合到输出节点的第二终端 以及电容元件，包括耦合到所述输出节点的第一端子和第二端子。 滤波器还包括反相门，其具有耦合到输入节点的第一端子和耦合到电容元件的第二端子的第二端子。

    Test circuit
    30.
    发明授权
    Test circuit 有权

    公开(公告)号：US11815547B2

    公开(公告)日：2023-11-14

    申请号：US17468377

    申请日：2021-09-07

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Francois Tailliet

    IPC: G01R31/28 ,  G01R1/067

    CPC classification number: G01R31/2884 ,  G01R1/06766 ,  G01R31/2889

    Abstract: A test circuit and a method for testing an integrated circuit are provided. The integrated circuit includes a test circuit. The test circuit includes a conductive track extending over at least a portion of the periphery of the integrated circuit, at least one component and an activation circuit adapted to deviating an input data signal into the conductive track during a test mode, and to transmitting the input data signal to the at least one component during a normal operating mode.

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