公开(公告)号：US20170323684A1

公开(公告)日：2017-11-09

申请号：US15659891

申请日：2017-07-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C16/0433 ,  G11C16/24

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

公开(公告)号：US09780098B2

公开(公告)日：2017-10-03

申请号：US15229709

申请日：2016-08-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Battista ,  François Tailliet

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C16/08 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  G11C14/00 ,  H01L21/8234

CPC classification number: H01L27/1104 ,  G11C11/4125 ,  G11C11/418 ,  G11C14/0063 ,  G11C16/045 ,  G11C16/08 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/513

Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

公开(公告)号：US09245624B2

公开(公告)日：2016-01-26

申请号：US14298264

申请日：2014-06-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C14/00 ,  G11C16/10

CPC classification number: G11C14/0063 ,  G11C16/10

Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Abstract translation: 存储器件包括至少一个具有第一SRAM型元件存储器单元的存储器单元，所述第一SRAM型元件存储器单元具有彼此交叉耦合的两个反相器和两组，每个具有至少一个非易失性基本存储器单元。 两组的非易失性基本存储单元首先通过可控制的互连级耦合到电源端子，其次耦合到两个反相器的输出端和输入端。

公开(公告)号：US20150270002A1

公开(公告)日：2015-09-24

申请号：US14657963

申请日：2015-03-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Battista ,  François Tailliet

IPC: G11C16/04 ,  H01L29/49 ,  H01L27/088 ,  H01L29/51 ,  G11C16/08 ,  G11C11/418

CPC classification number: H01L27/1104 ,  G11C11/4125 ,  G11C11/418 ,  G11C14/0063 ,  G11C16/045 ,  G11C16/08 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/513

Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

Abstract translation: 集成结构包括具有覆盖第一栅极电介质的第一可控栅极区域和与第一MOS晶体管相邻并且具有覆盖第一栅极电介质的第二可控栅极区域的第一MOS晶体管的第一MOS晶体管。 公共导电区域覆盖第一和第二栅极区域并且由第二栅极电介质分离。 公共导电区域包括位于第一和第二栅极区域的一部分上的连续元件以及从连续元件向衬底延伸至第一栅极电介质的分支。 位于第一和第二栅极区之间的分支。

公开(公告)号：US20150016188A1

公开(公告)日：2015-01-15

申请号：US14315401

申请日：2014-06-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C14/00

CPC classification number: G11C14/0063 ,  G11C7/1006 ,  G11C16/0408 ,  G11C16/3418

Abstract: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.

Abstract translation: 一种方法可用于管理包括彼此耦合的SRAM基本存储单元和非易失性基本存储单元的存储单元的操作。 数据位在SRAM单元存储单元和非易失性单元存储单元之间传送。 控制数据被存储在功能上类似于存储器单元并与其相关联的控制存储器单元中。 从SRAM基本存储单元读取数据位，并执行相应的控制数据读取。 如果控制数据具有第一值，则从SRAM基本存储器单元读取的数据位被反转，但是如果控制数据具有第二值，则从SRAM基本存储单元读取的数据位不反转。

公开(公告)号：US11488666B2

公开(公告)日：2022-11-01

申请号：US17157631

申请日：2021-01-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C7/00 ,  G11C14/00

Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node, and a single selection transistor coupled between the common node and a single bit line. A first output of the volatile memory cell is coupled to the common node, and a second output of the volatile memory cell, complementary to the first output, is not connected to any node outside the volatile memory cell.

公开(公告)号：US10706928B2

公开(公告)日：2020-07-07

申请号：US16043425

申请日：2018-07-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet ,  Marc Battista

IPC: G11C14/00 ,  G11C8/10 ,  G11C7/06 ,  G11C11/419 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24

Abstract: Disclosed herein is a method of operating a non-volatile static random access NVSRAM memory formed from words. Each word includes NVSRAM cells, each of those NVSRAM cells having an SRAM cell and an electronically erasable programmable read only memory EEPROM cell. If the SRAM cells of a word have been accessed since powerup, data is read from the NVSRAM cells of that word through the SRAM cells. However, if the SRAM cells of that word have not been written since powerup, data is read from the NVSRAM cells of that word through the EEPROM cells.

公开(公告)号：US10559575B2

公开(公告)日：2020-02-11

申请号：US16057193

申请日：2018-08-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  H01L27/11526 ,  G11C16/06 ,  H01L27/11524 ,  H01L27/11529 ,  G11C5/02 ,  G11C16/10 ,  G11C16/14

Abstract: A memory device includes a memory plane including a succession of neighboring semiconductor recesses of a first type of conductivity, wherein each semiconductor recess houses a plurality of memory words including a plurality of memory cells, wherein each memory cell includes a state transistor having a floating gate and a control gate. The memory device further includes a plurality of control gate selection transistors respectively allocated to each memory word of the plurality of memory words, wherein each control gate selection transistor is coupled to the control gates of the state transistors of the memory word to which the control gate selection transistor is allocated, wherein each control gate selection transistor is situated in and on a neighbor semiconductor recess of the semiconductor recess housing the memory word to which the control gate selection transistor is allocated.

公开(公告)号：US10403368B2

公开(公告)日：2019-09-03

申请号：US14849257

申请日：2015-09-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C5/02 ,  G11C8/08 ,  G11C8/10 ,  G11C16/14 ,  G11C16/08 ,  G11C8/12 ,  G11C8/14 ,  G11C16/04

Abstract: A non-volatile memory device includes a matrix memory plane with columns of memory words respectively formed on each row of the memory plane by groups of memory cells and control elements respectively associated with the memory words of each row. At least some of the control elements associated with the memory words of the corresponding row form at least one control block of B control elements disposed next to one another, adjacent to a memory block containing the B memory words disposed next to one another and associated with these B control elements, a first electrically-conducting link connecting one of the B control elements to all the control electrodes of the state transistors of the corresponding group of memory cells and B-1 second electrically-conducting link(s) respectively connecting the B-1 control element(s) to all the control electrodes of the state transistors of the B-1 corresponding group(s) of memory cells.

公开(公告)号：US10275173B2

公开(公告)日：2019-04-30

申请号：US15672475

申请日：2017-08-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F3/06 ,  G11C5/06 ,  G11C7/10 ,  G11C8/12

Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.