公开(公告)号：US20220262786A1

公开(公告)日：2022-08-18

申请号：US17670626

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisu Yu ,  Jungho Do ,  Jaewoo Seo ,  Hyeongyu You ,  Minjae Jeong

IPC: H01L27/02 ,  H01L27/118

Abstract: An integrated circuit including a first standard cell placed continuously on a row having a first height and a row having a second height different from the first height. The integrated circuit also includes a second standard cell continuously placed on a row having the first height and a row having the second height, a plurality of first power lines formed on boundaries of the plurality of rows and configured to supply a first supply voltage to the standard cells, and a plurality of second power lines formed on boundaries of the plurality of rows and configured to supply a second supply voltage to the standard cells. A placement sequence of the power lines supplying a voltage to the first standard cell being different from a placement sequence of the power lines supplying a voltage to the second standard cell.

公开(公告)号：US10916535B2

公开(公告)日：2021-02-09

申请号：US16727280

申请日：2019-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

IPC: H01L27/02 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  H01L27/118 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/092 ,  G06F30/398 ,  G06F119/18

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

公开(公告)号：US20180350791A1

公开(公告)日：2018-12-06

申请号：US15870143

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  G06F17/50 ,  G03F1/36

CPC classification number: H01L27/0207 ,  G03F1/36 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/092 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

公开(公告)号：US20240290692A1

公开(公告)日：2024-08-29

申请号：US18404529

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjae Jeong ,  Jungho Do ,  Jisu Yu

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: An integrated circuit includes standard cells on a front surface of a substrate, a front wiring layer extending in a first direction on the front surface of the substrate, and a backside wiring layer disposed on a rear surface of the substrate. A first standard cell of the standard cells includes a first gate line and a second gate line arranged apart from each other in the first direction to each extend in a second direction and power tap cells between the first and second gate lines, the power tap cells include a first power tap cell and a second power tap cell apart from the first power tap cell by a first interval in the first direction, and each of the first and second power tap cells is configured to electrically connect the backside wiring layer with the front wiring layer.

公开(公告)号：US20240250028A1

公开(公告)日：2024-07-25

申请号：US18397483

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungho DO ,  Jisu Yu ,  Hyeongyu You ,  Seungyoung Lee ,  Minjae Jeong

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/4175 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit may include gate electrodes including first and second gate electrodes being apart in a first direction and third and fourth gate electrodes being apart in the first direction. The second and third gate electrodes receive a first control signal, and the first and fourth gate electrodes receive a second control signal. The integrated circuit further includes a first drain region between the first and second gate electrodes and a second drain region between the third and fourth gate electrodes, wherein the first and second drain regions are electrically connected to each other. The integrated circuit includes a front-side wiring layer connected to at least one of the first and second drain regions and the first to fourth gate electrodes, and a backside wiring layer connected to at least another one of the first and second drain regions and the first to fourth gate electrodes.

公开(公告)号：US12019965B2

公开(公告)日：2024-06-25

申请号：US17225773

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu Yu ,  Jaeho Park ,  Sanghoon Baek ,  Hyeongyu You ,  Seungyoung Lee ,  Seungman Lim

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/528 ,  H01L29/423 ,  G06F117/12

CPC classification number: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/42376 ,  G06F2117/12

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

公开(公告)号：US20230378156A1

公开(公告)日：2023-11-23

申请号：US18303607

申请日：2023-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongyu You ,  Jisu Yu ,  Geonwoo Nam ,  Jungho Do ,  Minjae Jeong ,  Jaehee Cho

IPC: H01L27/02 ,  G06F30/31

CPC classification number: H01L27/0207 ,  G06F30/31

Abstract: An integrated circuit includes a first cell and a second cell respectively arranged in a first row and a second row that are adjacent to each other and extend in a first direction, and a third cell continuously arranged in the first row and the second row, wherein each of the first cell and the second cell comprises a first active pattern group including at least one active pattern that extends in the first direction and has a first conductivity type, the third cell comprises a second active pattern group including at least one active pattern that extends in the first direction in the first row and has the first conductivity type, and an effective channel width of the second active pattern group is greater than an effective channel width of the first active pattern group.

公开(公告)号：US11705456B2

公开(公告)日：2023-07-18

申请号：US17200179

申请日：2021-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Baek ,  Jungho Do ,  Jaewoo Seo ,  Jisu Yu

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/48

CPC classification number: H01L27/11807 ,  H01L23/481 ,  H01L27/0207 ,  H01L2027/11829 ,  H01L2027/11864 ,  H01L2027/11881

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

公开(公告)号：US20220059571A1

公开(公告)日：2022-02-24

申请号：US17200179

申请日：2021-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Baek ,  Jungho Do ,  Jaewoo Seo ,  Jisu Yu

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/48

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

公开(公告)号：US11152058B2

公开(公告)日：2021-10-19

申请号：US16566002

申请日：2019-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.