中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

71 records (took 0.03 seconds)

    Compensation film and display device including the same
    21.
    发明授权
    Compensation film and display device including the same 有权

    公开(公告)号：US10175404B2

    公开(公告)日：2019-01-08

    申请号：US15189631

    申请日：2016-06-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tsuyoshi Ohyama ,  Kitae Park ,  Hyunseok Choi ,  Koh Kamada

    IPC: G02B5/30 ,  G02F1/13363 ,  H01L27/32

    Abstract: An optical film includes a first compensation film and a second compensation film having a retardation for incident light different from the first compensation film, wherein the first compensation film includes a first liquid crystal layer including liquid crystals which are obliquely tilted relative to a surface of the first compensation film, and the second compensation film has a refractive index satisfying Relationship Equation 1 and Relationship Equation 2. nz2>nx2  Relationship Equation 1 nz2>ny2  Relationship Equation 2

    Sequentially accessing memory cells in a memory device
    25.
    发明授权
    Sequentially accessing memory cells in a memory device 有权
    顺序访问存储设备中的存储单元

    公开(公告)号：US09564234B2

    公开(公告)日：2017-02-07

    申请号：US14186474

    申请日：2014-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DongHun Kwak ,  Kitae Park ,  JinMan Han

    IPC: G11C16/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/24

    CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24

    Abstract: Systems and methods of sequentially accessing memory cells in a nonvolatile memory device (NVM) are provided. The NVM has a plurality of strings and a common signal line coupled to the plurality of strings. Each string includes a plurality of memory cells and a selection transistor coupled between the plurality of memory cells and the common signal line. A command that accesses multiple memory cells is received, a voltage is applied to a first selection transistor of a first string to electrically connect the common signal line to the first string, a pulse is applied for a predetermined time period to selection transistors of other strings, and memory cells of the first string are accessed. Advantages such as removal of boosting charges from unselected strings prior to sequentially accessing memory cells from selected strings can improve performance and reliability of NVM-based systems.

    Abstract translation: 提供了在非易失性存储器件（NVM）中顺序访问存储器单元的系统和方法。 NVM具有耦合到多个串的多个串和公共信号线。 每个串包括耦合在多个存储单元和公共信号线之间的多个存储单元和选择晶体管。 接收访问多个存储单元的命令，将电压施加到第一串的第一选择晶体管，以将公共信号线电连接到第一串，将脉冲施加预定时间段以选择其他串的晶体管 ，并且访问第一串的存储单元。 在从所选字符串顺序访问存储器单元之前，诸如从未选择的串去除升压电荷的优点可以提高基于NVM的系统的性能和可靠性。

    Storage device and a write method thereof
    26.
    发明授权
    Storage device and a write method thereof 有权
    存储装置及其写入方法

    公开(公告)号：US09336866B2

    公开(公告)日：2016-05-10

    申请号：US14188889

    申请日：2014-02-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： DongHun Kwak ,  Dongkyo Shim ,  Kitae Park ,  Hyun-Wook Park

    IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C16/349 ,  G11C16/3495

    Abstract: A write method of a storage device includes determining whether to perform a coarse program operation based on information about memory cells of a memory device, in response to a determination that the coarse program operation is to be performed, programming data in the memory device by performing the coarse program operation and a fine program operation, and in response to a determination that the coarse program operation is not to be performed, programming data in the memory device by performing the fine program operation.

    Abstract translation: 存储装置的写入方法包括响应于要执行粗略编程操作的确定，基于关于存储器件的存储器单元的信息来确定是否执行粗略编程操作，通过执行存储器件中的程序数据 粗程序操作和精细程序操作，并且响应于不执行粗程序操作的确定，通过执行精细程序操作来在存储器件中编程数据。

    Memory Systems and Block Copy Methods Thereof
    27.
    发明申请
    Memory Systems and Block Copy Methods Thereof 审中-公开
    内存系统及其复制方法

    公开(公告)号：US20150248328A1

    公开(公告)日：2015-09-03

    申请号：US14695375

    申请日：2015-04-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangyong Yoon ,  Kitae Park ,  Jinman Han

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1008 ,  G06F11/1072 ,  G11C29/52

    Abstract: Methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first “source” portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two (2). A second “target” portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using an address-scrambled reprogramming technique, for example.

    Abstract translation: 操作存储器系统和非易失性存储器件的方法包括在从非易失性存储器件中的M位非易失性存储器单元的第一“源”部分读取的M页数据上执行错误校验和校正（ECC）操作，从而产生M页的 ECC处理的数据，其中M是大于2（2）的正整数。 例如，非易失性存储器件中的M位非易失性存储单元的第二“目标”部分然后使用地址加扰的重新编程技术用ECC处理数据的M页被编程。

    Method for operating non-volatile memory device and memory controller
    28.
    发明授权
    Method for operating non-volatile memory device and memory controller 有权
    操作非易失性存储器件和存储器控制器的方法

    公开(公告)号：US09117536B2

    公开(公告)日：2015-08-25

    申请号：US14088511

    申请日：2013-11-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Jun Yoon ,  Jaeyong Jeong ,  Myung-Hoon Choi ,  Kitae Park

    IPC: G11C11/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3422

    Abstract: An operating method for a non-volatile memory device includes applying first and second read voltages to a first word line to perform a read operation; counting first memory cells each having a threshold voltage belonging to a first voltage range between the first read voltage and the second read voltage; applying a third read voltage to the first word line sequentially after applying the second read voltage to count second memory cells each having a second threshold voltage belonging to a voltage range between the second read voltage and the third read voltage; comparing the number of first memory cells counted and the number of second memory cells counted; determining a fourth read voltage based on a result of the comparing; and applying the fourth read voltage to the first word line sequentially after applying the third read voltage.

    Abstract translation: 一种用于非易失性存储器件的操作方法包括：将第一和第二读取电压施加到第一字线以执行读取操作; 计数每个具有属于第一读取电压和第二读取电压之间的第一电压范围的阈值电压的第一存储器单元; 在施加第二读取电压以对具有属于第二读取电压和第三读取电压之间的电压范围的第二阈值电压的第二存储器单元计数时，顺序地向第一字线施加第三读取电压; 比较计数的第一存储器单元的数量和计数的第二存储单元的数量; 基于所述比较的结果确定第四读取电压; 以及在施加第三读取电压之后，将第四读取电压顺序地施加到第一字线。

    Nonvolatile memory device with flag cells and user device including the same
    29.
    发明授权
    Nonvolatile memory device with flag cells and user device including the same 有权
    具有标志单元的非易失性存储器件和包括其的用户设备

    公开(公告)号：US08976592B2

    公开(公告)日：2015-03-10

    申请号：US13804128

    申请日：2013-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Soo Park ,  Kitae Park

    IPC: G11C11/34 ,  G11C16/28 ,  G11C11/56 ,  G11C16/34

    CPC classification number: G11C16/28 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3427 ,  G11C2211/5646

    Abstract: A nonvolatile memory device includes a flag cell configured to store flag information, a plurality of dummy cells adjacent to the flag cell, and program control logic configured to control a program operation on the flag cell and a dummy program operation on the plurality of dummy cells. When the program operation on the flag cell is performed, the program control logic performs the dummy program operation on at least one of the plurality of dummy cells.

    Abstract translation: 非易失性存储器件包括：标志单元，被配置为存储标志信息，与标志单元相邻的多个虚设单元;以及程序控制逻辑，被配置为控制对所述标志单元的编程操作，以及对所述多个虚设单元进行虚拟程序操作 。 当执行对标志单元的编程操作时，程序控制逻辑对多个虚设单元中的至少一个执行虚拟程序操作。

    Nonvolatile memory device and method of improving a program efficiency thereof
    30.
    发明授权
    Nonvolatile memory device and method of improving a program efficiency thereof 有权
    非易失性存储器件和提高其程序效率的方法

    公开(公告)号：US08958251B2

    公开(公告)日：2015-02-17

    申请号：US13913710

    申请日：2013-06-10

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Ohsuk Kwon ,  Sang-Hyun Joo ,  HyeongJun Kim ,  Kitae Park ,  Seung-Hwan Shin

    IPC: G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/24 ,  G11C16/3459

    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and configured to selectively pre-charge the plurality of bit lines, and control logic configured to control the page buffer circuit such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a first time at a read operation and such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a second time different from the first time at a verification read operation. The second time is determined on the basis of the number of selected bit lines of the plurality of bit lines at the verification read operation.

    Abstract translation: 非易失性存储器件包括包括多个存储器单元的存储单元阵列，经由多个位线与存储单元阵列连接并被配置为选择性地预充电多个位线的页缓冲器电路，以及配置为 控制页面缓冲器电路，使得在读取操作的第一时间期间将预充电电压施加到多个位线的选定位线，并且使得预充电电压被施加到多个位线中的选定位线 在第二时间不同于在验证读取操作的第一时间的位线。 基于在验证读取操作中的多个位线的选定位线的数量来确定第二次。

Patent Agency Ranking