公开(公告)号：US20170168931A1

公开(公告)日：2017-06-15

申请号：US15354354

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chankyung Kim ,  Uksong Kang ,  Sanguhn Cha ,  Sungyong Seo ,  Youngjin Cho ,  Seongil O

IPC: G06F12/02 ,  G11C14/00 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G06F12/0871 ,  G06F11/1064 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0853 ,  G06F12/0868 ,  G06F12/0895 ,  G06F2212/1004 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/313 ,  G06F2212/60 ,  G06F2212/601 ,  G06F2212/7203 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/005 ,  G11C11/4093 ,  G11C16/0483

Abstract: A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.

公开(公告)号：US11462255B2

公开(公告)日：2022-10-04

申请号：US17239854

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon Kwon ,  Jaeyoun Youn ,  Namsung Kim ,  Kyomin Sohn ,  Seongil O ,  Sukhan Lee

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/10

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

公开(公告)号：US11295805B2

公开(公告)日：2022-04-05

申请号：US17095008

申请日：2020-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Jongpil Son ,  Sanghyuk Kwon

IPC: G11C11/40 ,  G11C11/4078 ,  G11C11/408 ,  G06F21/75 ,  H01L25/065

Abstract: A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each semiconductor memory device includes a memory cell array to store data. The control device receives a command and an access address from an external device and provides the command and the access address to the semiconductor memory devices. Each semiconductor memory device performs an address swapping operation to randomly swap a portion of bits of the access address to generate a swapped address in response to a power-up signal or a reset signal, and enables a respective target word-line from among word-lines in the memory cell array such that two or more of the semiconductor memory devices enable different target word-lines in response to the access address.

公开(公告)号：US11281397B2

公开(公告)日：2022-03-22

申请号：US17009992

申请日：2020-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Kyomin Sohn

IPC: G06F3/06 ,  H01L25/065

Abstract: A stacked memory device includes a plurality memory semiconductor dies, a plurality of through silicon vias, a function-in-memory (FIM) front-end circuit and a plurality of FIM back-end circuits. The buffer semiconductor die is configured to communicate with a host device. The memory semiconductor dies are stacked on the buffer semiconductor die, and include a plurality of memory banks. The through-silicon vias electrically connect the buffer semiconductor die and the memory semiconductor dies. The FIM front-end circuit receives a plurality of FIM instructions for a FIM operation from the host device, and stores the FIM instructions. The FIM operation includes data processing based on internal data read from the memory banks. The FIM back-end circuits are respectively included in the memory semiconductor dies. The FIM back-end circuits perform the FIM operation corresponding to the plurality of FIM instructions stored in the FIM front-end circuit under control of the FIM front-end circuit.

公开(公告)号：US11276459B2

公开(公告)日：2022-03-15

申请号：US16996434

申请日：2020-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O

IPC: G06F13/00 ,  G11C11/4096 ,  H01L25/065 ,  G11C11/4091 ,  G06F13/16 ,  G06T1/60 ,  G10L15/28

Abstract: A memory die includes a first bank including first memory cells; a second bank including second memory cells; a first local processor connected with first bank local input/output lines through which first local bank data of the first bank are transmitted, and configured to execute a first local calculation on the first local bank data; a second local processor connected with second bank local input/output lines through which second local bank data of the second bank are transmitted, and configured to execute a second local calculation on the second local bank data; and a global processor configured to control the first bank, the second bank, the first local processor, and the second local processor and to execute a global calculation on a first local calculation result of the first local calculation and a second local calculation result of the second local calculation.

公开(公告)号：US11094371B2

公开(公告)日：2021-08-17

申请号：US16810344

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Shinhaeng Kang ,  Namsung Kim ,  Kyomin Sohn ,  Sukhan Lee

IPC: G11C11/409 ,  G11C11/4096 ,  G06N3/063 ,  G06N3/04 ,  G06F13/16

Abstract: A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.

公开(公告)号：US20210225429A1

公开(公告)日：2021-07-22

申请号：US16925049

申请日：2020-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Namsung KIM ,  Sukhan LEE

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10 ,  G06F9/30 ,  G06F9/38

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.

公开(公告)号：US20210224195A1

公开(公告)日：2021-07-22

申请号：US16995935

申请日：2020-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Seongil O

IPC: G06F12/1009 ,  G06F12/0895

Abstract: A memory controller includes a memory request queue that stores a memory request associated with a memory device including the first memory die and the second memory die having a shared channel, an address converter that selects one of first and second address mapping tables for the first memory die and the second memory die based on a bit of a physical address of the memory request and converts the physical address into a memory address based on the selected address mapping table and a physical layer that transmits the memory address to the memory device through the channel.

公开(公告)号：US20210217461A1

公开(公告)日：2021-07-15

申请号：US16994796

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4074

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US20200174749A1

公开(公告)日：2020-06-04

申请号：US16691033

申请日：2019-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Seongil O

IPC: G06F7/48 ,  G06F13/16 ,  G11C7/10

Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.