公开(公告)号：US11967623B2

公开(公告)日：2024-04-23

申请号：US17388233

申请日：2021-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Jung-Hwan Kim ,  Gukhyon Yon

IPC: H01L29/423 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/42344 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0657 ,  H01L29/42328 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Disclosed is a semiconductor device comprising gate stack structures on a substrate, separation structures extending in a first direction on the substrate and separating the gate stack structures, and vertical structures penetrating the gate stack structures. Each gate stack structure includes cell dielectric layers and electrodes including upper electrodes, a barrier layer extending between the electrodes and the cell dielectric layers, a separation dielectric pattern extending in the first direction and penetrating the upper electrodes to separate each upper electrode into pieces that are spaced apart from each other in a second direction intersecting the first direction, and capping patterns between the separation dielectric pattern and the upper electrodes. The capping patterns are on sidewalls of each upper electrode and spaced apart from each other in a third direction perpendicular to a top surface of the substrate. Each capping pattern is on a sidewall of the barrier layer.

公开(公告)号：US20240098996A1

公开(公告)日：2024-03-21

申请号：US18317274

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siyeong Yang ,  Sunggil Kim ,  Yuyeon Kim ,  Jumi Bak

IPC: H10B43/27 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2924/1431

Abstract: A three-dimensional semiconductor memory device may include a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure. The cell array structure may include a stack that includes interlayer insulating layers and conductive patterns alternately stacked with one another, a source structure on the stack, and a vertical structure that extends in the stack and is electrically connected to a bottom surface of the source structure. The vertical structure may include a channel layer that includes first portions respectively in vertical channel holes extending in the stack, and a second portion that extends in a region between the stack and the source structure and is electrically connected to the first portions.

公开(公告)号：US11910607B2

公开(公告)日：2024-02-20

申请号：US17881707

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H10B43/27 ,  H01L29/04 ,  H01L29/792 ,  H01L29/423 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L29/04 ,  H01L29/42344 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US11728246B2

公开(公告)日：2023-08-15

申请号：US17331951

申请日：2021-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil Kim ,  Jinhyuk Kim ,  Jung-Hwan Kim

IPC: H01L29/78 ,  H01L23/48 ,  H01L25/065 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/481 ,  H01L25/0652 ,  H01L29/7827 ,  H10B41/27 ,  H10B43/27 ,  H01L2225/06541

Abstract: A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.

公开(公告)号：US11626414B2

公开(公告)日：2023-04-11

申请号：US16903026

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim

IPC: H01L27/11568 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/11582 ,  G11C5/02

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.

公开(公告)号：US11424264B2

公开(公告)日：2022-08-23

申请号：US16838586

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/792 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US11387253B2

公开(公告)日：2022-07-12

申请号：US16910199

申请日：2020-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Junghwan Kim ,  Chanhyoung Kim

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10

Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conductive layer has an extension portion extending along a surface of the vertical channel layer in the extended area of the vertical structure.

公开(公告)号：US20220181458A1

公开(公告)日：2022-06-09

申请号：US17388233

申请日：2021-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Jung-Hwan Kim ,  Gukhyon Yon

IPC: H01L29/423 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/48

Abstract: Disclosed is a semiconductor device comprising gate stack structures on a substrate, separation structures extending in a first direction on the substrate and separating the gate stack structures, and vertical structures penetrating the gate stack structures. Each gate stack structure includes cell dielectric layers and electrodes including upper electrodes, a barrier layer extending between the electrodes and the cell dielectric layers, a separation dielectric pattern extending in the first direction and penetrating the upper electrodes to separate each upper electrode into pieces that are spaced apart from each other in a second direction intersecting the first direction, and capping patterns between the separation dielectric pattern and the upper electrodes. The capping patterns are on sidewalls of each upper electrode and spaced apart from each other in a third direction perpendicular to a top surface of the substrate. Each capping pattern is on a sidewall of the barrier layer.

公开(公告)号：US20210098480A1

公开(公告)日：2021-04-01

申请号：US16903026

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  G11C5/06

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.

公开(公告)号：US10930739B2

公开(公告)日：2021-02-23

申请号：US16186915

申请日：2018-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Dongkyum Kim ,  Sunggil Kim ,  Seulye Kim ,  Sangsoo Lee ,  Hyeeun Hong

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.