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    INTEGRATED CIRCUITS INCLUDING STANDARD CELLS AND METHODS OF MANUFACTURING THE INTEGRATED CIRCUITS
    21.
    发明申请
    INTEGRATED CIRCUITS INCLUDING STANDARD CELLS AND METHODS OF MANUFACTURING THE INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20200050728A1

    公开(公告)日：2020-02-13

    申请号：US16378751

    申请日：2019-04-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JIN-TAE KIM ,  Sung-We Cho ,  Tae-Joong Song ,  Seung-Young Lee ,  Jin-Young Lim

    IPC: G06F17/50 ,  H01L27/02

    Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.

    Method and system for designing semiconductor device
    23.
    发明授权
    Method and system for designing semiconductor device 有权

    公开(公告)号：US09842182B2

    公开(公告)日：2017-12-12

    申请号：US14845556

    申请日：2015-09-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Tae-Joong Song ,  Gi-Young Yang ,  Jeong-Ho Do

    IPC: G06F17/50 ,  H01L29/66

    CPC classification number: G06F17/5072 ,  G06F17/5081 ,  H01L29/6681

    Abstract: A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    25.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150137262A1

    公开(公告)日：2015-05-21

    申请号：US14465968

    申请日：2014-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kang-Hyun Baek ,  Sung-Hyun Park ,  Sang-Hoon Baek ,  Tae-Joong Song

    IPC: H01L29/78 ,  H01L27/11

    CPC classification number: H01L29/785 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/66818

    Abstract: A semiconductor device includes: active fins protruding from an active layer and extending in a first direction; a gate structure on the active fins extending in a second direction intersecting the first direction; and a spacer on at least one side of the gate structure, wherein each of the active fins includes a first region and a second region adjacent to the first direction in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction.

    Abstract translation: 半导体器件包括：从有源层突出并沿第一方向延伸的有源鳍; 主动翅片上的栅极结构沿与第一方向相交的第二方向延伸; 以及在所述栅极结构的至少一侧上的间隔物，其中所述活性鳍片中的每一个包括第一区域和与所述第一方向上的所述第一方向相邻的第二区域，并且所述第一区域在所述第二方向上的宽度不同 从第二方向的第二区域的宽度。

    Resistive memory device having reduced chip size and operation method thereof
    30.
    发明授权
    Resistive memory device having reduced chip size and operation method thereof 有权

    公开(公告)号：US10600466B2

    公开(公告)日：2020-03-24

    申请号：US16450035

    申请日：2019-06-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Suk-Soo Pyo ,  Hyun-Taek Jung ,  Tae-Joong Song

    IPC: G11C11/00 ,  G11C11/16 ,  G11C8/08 ,  G11C13/00 ,  G11C11/56

    Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.

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