公开(公告)号：US12020767B2

公开(公告)日：2024-06-25

申请号：US17539761

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-Soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1048 ,  G11C7/1084 ,  G11C7/222

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US20200227130A1

公开(公告)日：2020-07-16

申请号：US16574808

申请日：2019-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Heung Kim ,  Kyo-Min Sohn ,  Young-Soo Sohn

IPC: G11C29/38 ,  H01L25/065 ,  G11C11/4076 ,  G11C29/12

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

公开(公告)号：US09589674B2

公开(公告)日：2017-03-07

申请号：US14305095

申请日：2014-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Young-Soo Sohn ,  Uk-Song Kang ,  Chul-Woo Park ,  Jung-Hwan Choi ,  Won-Il Bae ,  Kyo-Min Sohn

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract translation: 在操作存储器件的方法中，接收来自存储器控制器的命令和第一地址。 从存储器件的存储单元阵列读取包括对应于第一地址的第一组数据，对应于第二地址的第二组数据和读取奇偶校验数据的读码字。 通过使用基于读取的线字的ECC电路的操作错误检查和校正（ECC）来生成校正的数据。

公开(公告)号：US09235466B2

公开(公告)日：2016-01-12

申请号：US13915179

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo Sohn ,  Chul-Woo Park ,  Jong-Pil Son ,  Jung-bae Lee

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/37 ,  G11C29/04

CPC classification number: G06F11/1012 ,  G06F11/10 ,  G06F11/1024 ,  G06F11/1048 ,  G06F11/106 ,  G11C2029/0411 ,  H03M13/3707

Abstract: An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.

Abstract translation: 纠错装置包括：纠错电路，被配置为对存储器件的多个存储单元的至少一个写入和读出的数据的一部分进行选择性地执行纠错。 数据的部分是从多个存储器单元的子集写入和读出中的至少一个，并且该子集仅包括多个存储器单元中的故障单元。 误差校正装置还包括故障地址存储电路，其被配置为存储故障单元的地址信息。

公开(公告)号：US09087614B2

公开(公告)日：2015-07-21

申请号：US14087167

申请日：2013-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Uk-Song Kang ,  Chul-Woo Park ,  Young-Soo Sohn

IPC: G11C7/12 ,  G11C29/44 ,  G06F11/10 ,  G11C29/00 ,  G11C5/04 ,  G11C29/04

CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.

Abstract translation: 在一个示例实施例中，存储器模块包括多个存储器件和被配置为管理多个存储器件的缓冲器芯片。 缓冲器芯片包括具有错误校正单元的存储器管理单元，该单元被配置为对多个存储器件中的每一个进行纠错操作。 多个存储器设备中的每一个包括至少一个可由存储器管理单元访问的备用列，并且存储器管理单元被配置为通过有选择地使用至少一个备用列来校正多个存储器件的错误， 纠错单元的纠错能力。

公开(公告)号：US09007856B2

公开(公告)日：2015-04-14

申请号：US13804690

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Jae-Sung Kim ,  Uk-Song Kang ,  Young-Soo Sohn

IPC: G11C7/00 ,  G11C29/04 ,  G11C29/44

CPC classification number: G11C29/04 ,  G11C29/806 ,  G11C29/808 ,  G11C2029/4402

Abstract: A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not.

Abstract translation: 控制半导体存储器件的修复操作的修复控制电路包括行匹配块和列匹配块。 行匹配块存储指示多个行组中的一个或多个故障行组的故障组信息。 通过对与多个字线对应的多个行地址进行分组来确定行组。 行匹配块基于输入行地址和故障组信息生成组匹配信号，使得组匹配信号指示包括输入行地址的故障行组。 列匹配块存储故障存储器单元的故障列地址，并且基于输入列地址，组匹配信号和故障列地址生成修复控制信号，使得修复控制信号指示是否执行修复操作或 不。