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74 条记录 (耗时 0.035 秒)

    Semiconductor device with reduced memory leakage current
    21.
    发明授权
    Semiconductor device with reduced memory leakage current 有权
    具有减少内存泄漏电流的半导体器件

    公开(公告)号：US07095074B2

    公开(公告)日：2006-08-22

    申请号：US10196166

    申请日：2002-07-17

    申请人： Keisuke Tsukamoto ,  Yoshihiro Ikeda ,  Tsutomu Okazaki ,  Daisuke Okada ,  Hiroshi Yanagita

    发明人： Keisuke Tsukamoto ,  Yoshihiro Ikeda ,  Tsutomu Okazaki ,  Daisuke Okada ,  Hiroshi Yanagita

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

    摘要： Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.

    摘要翻译： 在其上形成非易失性存储器的存储单元的元件形成区域中的缺陷将被减小以减少泄漏电流。 在其上形成有非易失性存储单元的元件形成区域的端部通过利用虚设导电膜下面的区域而延伸长度D，由此围绕元件形成区域的绝缘膜引起的应力集中在延伸区域上 。 结果，缺陷不延伸到形成存储单元的区域，因此可以减少存储单元中的漏电流。

    Nonvolatile memory device and semiconductor device
    22.
    发明授权
    Nonvolatile memory device and semiconductor device 有权
    非易失性存储器件和半导体器件

    公开(公告)号：US07085157B2

    公开(公告)日：2006-08-01

    申请号：US10805365

    申请日：2004-03-22

    申请人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    发明人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0433

    摘要： A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 ìA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 ìA to flow a current in the memory cell.

    摘要翻译： 一种用于通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入和降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1AA的恒定电流，并且通过约1μA的恒定电流放电位线以使存储器单元中的电流流动。

    Nonvolatile semiconductor device and method of manufacturing the same
    23.
    发明授权
    Nonvolatile semiconductor device and method of manufacturing the same 有权
    非易失性半导体器件及其制造方法

    公开(公告)号：US08796756B2

    公开(公告)日：2014-08-05

    申请号：US13755348

    申请日：2013-01-31

    申请人： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasafumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

    发明人： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasafumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

    IPC分类号： H01L29/792

    CPC分类号： H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

    摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

    摘要翻译： 插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为 小于40nm。 因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。 此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

    Image forming apparatus, and computer program product for image forming provided with managing log of a time designated print job
    24.
    发明授权
    Image forming apparatus, and computer program product for image forming provided with managing log of a time designated print job 有权
    图像形成装置和用于图像形成的计算机程序产品，其具有指定时间指定打印作业的管理日志

    公开(公告)号：US08582161B2

    公开(公告)日：2013-11-12

    申请号：US13137297

    申请日：2011-08-04

    申请人： Daisuke Okada ,  Noboru Tamura ,  Nobuhiro Shindo ,  Hideaki Matsui ,  Hajime Kubota ,  Yuto Shibata ,  Takeo Momose ,  Masahiro Hayashi

    发明人： Daisuke Okada ,  Noboru Tamura ,  Nobuhiro Shindo ,  Hideaki Matsui ,  Hajime Kubota ,  Yuto Shibata ,  Takeo Momose ,  Masahiro Hayashi

    IPC分类号： G06F3/12 ,  G06K15/02

    CPC分类号： G06F3/1239 ,  G06F3/1212 ,  G06F3/1222 ,  G06F3/1267 ,  G06F3/1273 ,  G06F3/1274 ,  G06F3/1279

    摘要： An image forming apparatus includes a receiving unit; a data saving unit; a drawing data generating unit; a log storage unit that stores a processing log; an image forming unit; and a data management unit. The data management unit, when the print job is analyzed as a time designated print job; causes the data generating unit to generate the drawing data; causes the data saving unit to save the drawing data; that, when analyzed printing being enabled at the designated print time, causes the image forming unit to perform image formation based on the drawing data and causes the log storage unit to store therein a processing log; and that, when printing is analyzed as disabled at the designated print time, performs processing corresponding to a print disabled state preset and causes the log storage unit to store therein a processing log about the processing.

    摘要翻译： 图像形成装置包括：接收单元; 数据保存单元; 绘图数据生成单元; 存储处理日志的日志存储单元; 图像形成单元; 和数据管理单元。 当打印作业被分析为时间指定打印作业时，数据管理单元; 使数据生成单元生成绘图数据; 使数据保存单元保存绘图数据; 当在指定的打印时间分析打印被启用时，使图像形成单元基于绘图数据执行图像形成，并使日志存储单元在其中存储处理日志; 并且当在指定的打印时间将打印分析为禁用时，执行与打印禁用状态预设相对应的处理，并且使日志存储单元在其中存储关于处理的处理日志。

    Semiconductor nonvolatile memory device
    26.
    发明授权
    Semiconductor nonvolatile memory device 有权
    半导体非易失性存储器件

    公开(公告)号：US08472258B2

    公开(公告)日：2013-06-25

    申请号：US13269425

    申请日：2011-10-07

    申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

    摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

    摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

    SEMICONDUCTOR NONVOLATILE MEMORY DEVICE
    28.
    发明申请
    SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
    半导体非易失性存储器件

    公开(公告)号：US20120026798A1

    公开(公告)日：2012-02-02

    申请号：US13269425

    申请日：2011-10-07

    申请人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    发明人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    IPC分类号： G11C16/10

    CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

    摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

    摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

    Semiconductor nonvolatile memory device
    29.
    发明授权
    Semiconductor nonvolatile memory device 有权
    半导体非易失性存储器件

    公开(公告)号：US08064261B2

    公开(公告)日：2011-11-22

    申请号：US12787158

    申请日：2010-05-25

    申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

    摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

    摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅结构的半导体非易失性存储器件中进行热孔注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

    SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF
    30.
    发明申请
    SEMICONDUCTOR DEVICE HAVING ELECTRODE AND MANUFACTURING METHOD THEREOF 失效
    具有电极的半导体器件及其制造方法

    公开(公告)号：US20110014783A1

    公开(公告)日：2011-01-20

    申请号：US12888995

    申请日：2010-09-23

    申请人： Tsutomu OKAZAKI ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

    发明人： Tsutomu OKAZAKI ,  Motoi Ashida ,  Hiroji Ozaki ,  Tsuyoshi Koga ,  Daisuke Okada

    IPC分类号： H01L21/283

    CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

    摘要： A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

    摘要翻译： 半导体器件的制造方法包括：第一电极形成步骤，在控制栅电极和半导体衬底之间形成控制栅极电极，该控制栅电极在半导体衬底的表面上方，控制栅绝缘膜，形成存储节点 绝缘膜，以及在存储节点绝缘膜的表面上形成存储栅电极的第二电极形成步骤。 第二电极形成步骤包括在存储节点绝缘膜的表面上形成存储栅极电极层的步骤，在表面上形成蚀刻速率慢于存储栅电极层的蚀刻速率的辅助膜的步骤 的存储栅电极层和对存储栅电极层和辅助膜进行各向异性蚀刻的步骤。