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    Imaging architecture with code-division multiplexing for large aperture arrays
    23.
    发明授权
    Imaging architecture with code-division multiplexing for large aperture arrays 有权
    具有用于大孔径阵列的码分复用的成像架构

    公开(公告)号：US09030354B2

    公开(公告)日：2015-05-12

    申请号：US13417559

    申请日：2012-03-12

    Applicant: Arun Natarajan ,  Scott Reynolds

    Inventor： Arun Natarajan ,  Scott Reynolds

    IPC: G01S3/02 ,  H04W88/08 ,  H04B1/50

    CPC classification number: H04W88/08 ,  G01S3/46 ,  G01S7/352 ,  G01V8/005 ,  G01V8/20 ,  H04B1/50

    Abstract: A method and structure for a phased-array system. An orthogonal signal generator generates a plurality of signals C(i) that are orthogonal or near-orthogonal, meaning that a cross correlation between any two signals C(i) is lower than autocorrelation, and there is a plurality of phased-array antenna elements, each said antenna element providing a signal Sinp(i). A multiplier multiplies each signal C(i) with the signal Sinp(i) of a corresponding one of the plurality of phased array antenna elements.

    Abstract translation: 一种相控阵系统的方法和结构。 正交信号发生器产生正交或近正交的多个信号C（i），这意味着任何两个信号C（i）之间的互相关低于自相关，并且存在多个相控阵天线元件 ，每个所述天线元件提供信号Sinp（i）。 乘法器将每个信号C（i）与多个相控阵列天线元件中相应一个的信号Sinp（i）相乘。

    Method and system for measuring carbon dioxide reduction
    24.
    发明申请
    Method and system for measuring carbon dioxide reduction 审中-公开
    测量二氧化碳减少的方法和系统

    公开(公告)号：US20100287012A1

    公开(公告)日：2010-11-11

    申请号：US12078926

    申请日：2008-04-08

    Applicant: Arne Ballantine ,  Ian Russell ,  Scott Reynolds

    Inventor： Arne Ballantine ,  Ian Russell ,  Scott Reynolds

    IPC: G06Q10/00 ,  G06F19/00 ,  G01R21/00 ,  G06F17/30 ,  G06Q30/00

    CPC classification number: G06Q10/06 ,  G06Q10/30 ,  Y02P90/84 ,  Y02P90/845 ,  Y02W90/20

    Abstract: A system and method is provided for managing energy data. The system includes a energy transformation device, a central energy data management system and a database containing carbon dioxide credit information. Managing the energy data includes measuring an amount of power produced or consumed by an energy transformation device, measuring an amount of carbon dioxide emitted, converted or sequestered by the energy transformation device, creating a dataset of the power produced or consumed and the amount of carbon dioxide emitted or sequestered, and transmitting the dataset and characteristic data to a central energy data management system. The method also includes, receiving energy measurements and characteristic data from an energy transformation device, obtaining carbon dioxide credit information and comparing the received energy measurements and the characteristic data with the received carbon dioxide credit information to obtain a carbon dioxide credit for the energy transformation device.

    Abstract translation: 提供了一种用于管理能量数据的系统和方法。 该系统包括能量转换装置，中央能量数据管理系统和包含二氧化碳信用信息的数据库。 管理能源数据包括测量能量转换装置产生或消耗的功率量，测量由能量转换装置发射，转换或隔离的二氧化碳的量，创建产生或消耗的功率的数据集和碳量 二氧化碳排放或隔离，并将数据集和特征数据传输到中央能量数据管理系统。 该方法还包括从能量转换装置接收能量测量和特征数据，获得二氧化碳信用信息并将接收到的能量测量和特征数据与接收的二氧化碳信用信息进行比较，以获得能量转换装置的二氧化碳信用 。

    SYSTEM AND METHODS FOR SEQUENCING LEARNING OBJECTS BASED UPON QUERY AND USER RELEVANCY
    26.
    发明申请
    SYSTEM AND METHODS FOR SEQUENCING LEARNING OBJECTS BASED UPON QUERY AND USER RELEVANCY 失效
    基于查询和用户相关性的学习对象序列的系统和方法

    公开(公告)号：US20090197237A1

    公开(公告)日：2009-08-06

    申请号：US12025455

    申请日：2008-02-04

    Applicant: Jacob Couch ,  Curtis Stratman ,  Jeremy Espenshade ,  Scott Reynolds

    Inventor： Jacob Couch ,  Curtis Stratman ,  Jeremy Espenshade ,  Scott Reynolds

    IPC: G09B7/00

    CPC classification number: G09B7/08

    Abstract: A system for generating a sequence of learning objects comprising an e-Learning course is provided. The system can include one or more processors and a memory unit for electronically storing data comprising a plurality of learning objects. The system further can include a sequence builder configured to execute on the at least one processor. The sequence builder, more particularly, can be configured to generate a sequence comprising at least a portion of the plurality of learning objects based upon a measurable user relevancy and/or a measurable query relevancy of each learning object contained in the sequence.

    Abstract translation: 提供了一种用于生成包括电子学习课程的学习对象序列的系统。 该系统可以包括一个或多个处理器和用于电子地存储包括多个学习对象的数据的存储器单元。 系统还可以包括被配置为在至少一个处理器上执行的序列构建器。 更具体地，序列构建器可以被配置为基于包含在序列中的每个学习对象的可测量的用户相关性和/或可测量的查询相关性来生成包括多个学习对象的至少一部分的序列。

    INTEGRATED MILLIMETER-WAVE QUADRATURE GENERATOR
    28.
    发明申请
    INTEGRATED MILLIMETER-WAVE QUADRATURE GENERATOR 审中-公开
    集成式毫米波瓦斯发电机

    公开(公告)号：US20080051054A1

    公开(公告)日：2008-02-28

    申请号：US11930471

    申请日：2007-10-31

    Applicant: Brian Floyd ,  Ullrich Pfeiffer ,  Scott Reynolds ,  Thomas Zwick

    Inventor： Brian Floyd ,  Ullrich Pfeiffer ,  Scott Reynolds ,  Thomas Zwick

    IPC: H04B1/26

    CPC classification number: H04B1/30

    Abstract: An off-chip signal is provided to a differential branch-line directional coupler implemented entirely on-chip. The coupler produces differential quadrature signals, which are then buffered and applied to a quadrature mixer. The coupler is implemented entirely on-chip using microstrip transmission lines. The coupler is made up of a plurality of rings and a plurality of underpasses connecting ports of the rings, wherein each of the plurality of rings is made up of four branch lines, and each branch line having an electrical length of one-quarter wavelength at the center design frequency. Coupling between the plurality of branch lines of the rings may be varied.

    Abstract translation: 片外信号被提供给完全在芯片上实现的差分分支线定向耦合器。 耦合器产生差分正交信号，然后缓冲并施加到正交混频器。 耦合器使用微带传输线完全在片上实现。 耦合器由多个环和连接多个环的端口的多个地下通道组成，其中多个环中的每一个环由四个分支线构成，并且每个分支线具有四分之一波长的电长度 中心设计频率。 可以改变环的多个分支线之间的耦合。

    Apparatus and method for signal phase control in an integrated radio circuit
    29.
    发明申请
    Apparatus and method for signal phase control in an integrated radio circuit 审中-公开
    集成无线电电路中信号相位控制的装置和方法

    公开(公告)号：US20070160168A1

    公开(公告)日：2007-07-12

    申请号：US11329512

    申请日：2006-01-11

    Applicant: Troy Beukema ,  Brian Floyd ,  Scott Reynolds ,  Sergey Rylov

    Inventor： Troy Beukema ,  Brian Floyd ,  Scott Reynolds ,  Sergey Rylov

    IPC: H04L27/00 ,  H03D1/04

    CPC classification number: H04L27/2273 ,  H04L1/206 ,  H04L27/0014 ,  H04L2027/0057

    Abstract: An apparatus and method to control signal phase in a radio device includes a phase rotator configured to control a phase of a local oscillator. A phase error determination module is configured to determine phase error information based on received in-phase (I) and quadrature (Q) (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.

    Abstract translation: 控制无线电设备中的信号相位的装置和方法包括配置成控制本地振荡器的相位的相位旋转器。 相位误差确定模块被配置为基于接收到的同相（I）和正交（Q）（IQ）信号值来确定相位误差信息。 相位校正模块被配置为从所接收的IQ信号值导出校正信号，并将校正信号施加到本地振荡器的路径中的相位旋转器。

    Integrated spectrum analyzer circuits and methods for providing on-chip diagnostics
    30.
    发明申请
    Integrated spectrum analyzer circuits and methods for providing on-chip diagnostics 失效
    用于提供片上诊断功能的集成频谱分析仪电路和方法

    公开(公告)号：US20060025946A1

    公开(公告)日：2006-02-02

    申请号：US10900733

    申请日：2004-07-28

    Applicant: Keith Jenkins ,  Anup Jose ,  Scott Reynolds

    Inventor： Keith Jenkins ,  Anup Jose ,  Scott Reynolds

    IPC: G01R23/16

    CPC classification number: G01R23/16 ,  G01R23/20 ,  G01R31/316 ,  G01R31/3167

    Abstract: Spectrum analyzer circuits and methods are provided which implement “zero-IF” (direct conversion) or “near-zero IF” (or very low IF) architectures that enable implementation of integrated (on-chip) spectrum analyzers for measuring the frequency spectrum of internal chip signals. An integrated spectrum analyzer circuit, which comprises a zero IF or near-zero IF framework, enables a low-power compact design with sufficient resolution bandwidth for on-chip implementation and diagnostics of internal chip signals.

    Abstract translation: 提供了实现“零中频”（直接转换）或“近零中频”（或非常低的IF）架构的频谱分析仪电路和方法，其能够实现集成（片上）频谱分析仪，用于测量频谱 内部芯片信号。 包含零中频或近零IF框架的集成频谱分析仪电路实现了低功耗紧凑设计，具有足够的分辨率带宽，用于片内实现和内部芯片信号的诊断。

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