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42 条记录 (耗时 0.025 秒)

    Method of forming semiconductor devices by microwave curing of low-k dielectric films
    21.
    发明授权
    Method of forming semiconductor devices by microwave curing of low-k dielectric films 有权
    通过低k介电膜的微波固化形成半导体器件的方法

    公开(公告)号：US07557035B1

    公开(公告)日：2009-07-07

    申请号：US10849847

    申请日：2004-05-21

    申请人： E. Todd Ryan ,  John A. Iacoponi

    发明人： E. Todd Ryan ,  John A. Iacoponi

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76825 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/76813

    摘要： The invention provides a method of exposing low-k dielectric films to microwave radiation to cure the dielectric films. Microwave curing reduces the cure-time necessary to achieve the desired mechanical properties in the low-k films, thus decreasing the thermal exposure time for the NiSi transistor contacts. A lower thermal budget for interconnect fabrication is necessary to prevent damage to the NiSi transistor contacts and minimize thermal stressing of previously formed interconnect layers. Microwave-cured dielectric films also have higher mechanical strength and strong adhesion to overlying layers deposited during subsequent semiconductor device manufacturing steps.

    摘要翻译： 本发明提供了一种将低k电介质膜暴露于微波辐射以固化电介质膜的方法。 微波固化降低了在低k膜中实现所需机械性能所需的固化时间，从而降低了NiSi晶体管触点的热曝光时间。 为了防止损坏NiSi晶体管触点并最小化先前形成的互连层的热应力，需要用于互连制造的较低热预算。 微波固化的介电膜对随后的半导体器件制造步骤期间沉积的上覆层也具有较高的机械强度和强粘合性。

    Test structure for providing depth of polish feedback
    22.
    发明授权
    Test structure for providing depth of polish feedback 失效
    提供抛光反馈深度的测试结构

    公开(公告)号：US06514858B1

    公开(公告)日：2003-02-04

    申请号：US09829202

    申请日：2001-04-09

    申请人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

    发明人： Frederick N. Hause ,  Paul R. Besser ,  Frank Mauersberger ,  Errol Todd Ryan ,  William S. Brennan ,  John A. Iacoponi ,  Peter J. Beckage

    IPC分类号： H01L214763

    CPC分类号： H01L22/34 ,  B24B37/042 ,  B24B49/00 ,  H01L21/31053 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

    摘要翻译： 提供了一种用于控制半导体器件的抛光工艺的测试结构。 测试结构由结构层，第一处理层和互连构成。 第一处理层位于结构层上方，并且具有形成在其中并且至少部分地穿过其延伸到预选深度的多个开口。 多个开口的至少一部分具有在从第一处理层朝向结构层的方向上逐渐变窄的锥形区域。 开口间隔开预定距离X. 互连形成在包括锥形区域的多个开口中。 因此，当通过抛光工艺去除工艺层和互连件时，距离X增加，表示抛光过程的深度。

    Creation of an etch hardmask by spin-on technique
    24.
    发明授权
    Creation of an etch hardmask by spin-on technique 失效
    通过旋转技术创建蚀刻硬掩模

    公开(公告)号：US06218078B1

    公开(公告)日：2001-04-17

    申请号：US08936276

    申请日：1997-09-24

    申请人： John A. Iacoponi

    发明人： John A. Iacoponi

    IPC分类号： G03F700

    CPC分类号： H01L21/0332 ,  H01L21/31144

    摘要： A system and method for etching structures in a layer of a semiconductor device are disclosed. The method and system include spinning-on a hardmask layer, patterning the hardmask layer, and etching the layer. The hardmask layer is disposed above the layer and has a high etch selectivity.

    摘要翻译： 公开了一种用于蚀刻半导体器件层中的结构的系统和方法。 该方法和系统包括旋涂硬掩模层，图案化硬掩模层和蚀刻该层。 硬掩模层设置在层上方并具有高蚀刻选择性。

    Metal-semiconductor contact formed using nitrogen plasma
    25.
    发明授权
    Metal-semiconductor contact formed using nitrogen plasma 失效
    使用氮等离子体形成的金属 - 半导体接触

    公开(公告)号：US5912508A

    公开(公告)日：1999-06-15

    申请号：US715140

    申请日：1996-09-18

    申请人： John A. Iacoponi

    发明人： John A. Iacoponi

    IPC分类号： H01L21/285 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/28518

    摘要： A low-resistance metal-semiconductor contact for use in integrated circuits includes a titanium silicide layer overlaying a semiconductor body. The top surface of the titanium silicide layer is a combination of silicides and titanium nitride formed by exposing the top surface to a nitrogen plasma. This combination surface is covered by a layer of titanium nitride, which is in turn covered by a layer of conductive metal, such as tungsten.

    摘要翻译： 用于集成电路的低电阻金属 - 半导体触点包括覆盖半导体本体的钛硅化物层。 硅化钛层的顶表面是通过将顶表面暴露于氮等离子体而形成的硅化物和氮化钛的组合。 该组合表面被一层氮化钛覆盖，氮化钛层又由诸如钨的导电金属层覆盖。

    Method for depositing a conductive capping layer on metal lines
    26.
    发明授权
    Method for depositing a conductive capping layer on metal lines 有权
    在金属线上沉积导电覆盖层的方法

    公开(公告)号：US08592312B2

    公开(公告)日：2013-11-26

    申请号：US11811418

    申请日：2007-06-07

    申请人： E. Todd Ryan ,  John A. Iacoponi

    发明人： E. Todd Ryan ,  John A. Iacoponi

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76849

    摘要： In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.

    摘要翻译： 在一个公开的实施例中，用于在金属线上沉积导电覆盖层的本方法包括在电介质层上形成金属线，向金属线施加电压，以及在金属线上沉积导电覆盖层。 施加的电压增加了所使用的沉积工艺的选择性，从而防止导电覆盖层在金属线之间引起短路。 导电覆盖层可通过电镀，无电解，原子层沉积（ALD）或化学气相沉积（CVD）沉积。 在一个实施例中，本方法用于制造半导体晶片。 在一个实施例中，金属线包括铜线，而导电覆盖层可以包括钽或钴。 本方法能够沉积具有高耐迁移性的覆盖层。

    Strength coil for ionized copper plasma deposition
    30.
    发明授权
    Strength coil for ionized copper plasma deposition 失效
    电离铜等离子体沉积强度线圈

    公开(公告)号：US06244210B1

    公开(公告)日：2001-06-12

    申请号：US09430452

    申请日：1999-10-29

    申请人： John A. Iacoponi ,  Paul R. Besser

    发明人： John A. Iacoponi ,  Paul R. Besser

    IPC分类号： C23C1600

    CPC分类号： H01J37/321 ,  C23C14/358

    摘要： A new type of plasma coil for use in ionized metal plasma deposition systems. This new coil provides significant added strength to prevent sagging or other mechanical deformation. The improved coil consists of a core of a high strength material such as Titanium, for example. The rigid core is surrounded on all sides by a layer of pure copper. The rigid core could be made of other refractory metals. A Titanium copper alloy core could be used and would bind the Titanium to the copper within the core to prevent it from diffusing or reacting with the pure copper outer layer.

    摘要翻译： 一种用于电离金属等离子体沉积系统的新型等离子体线圈。 这种新的线圈提供了显着的附加强度，以防止下垂或其他机械变形。 改进的线圈例如由诸如钛的高强度材料的芯组成。 刚性芯在各个面都被一层纯铜包围。 刚性芯可以由其他难熔金属制成。 可以使用钛铜合金芯，并且将钛结合到芯内的铜以防止其与纯铜外层扩散或反应。