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42 条记录 (耗时 0.019 秒)

    Method and apparatus for enhancing endpoint detection of a via etch
    5.
    发明授权
    Method and apparatus for enhancing endpoint detection of a via etch 有权
    用于增强通孔蚀刻的端点检测的方法和装置

    公开(公告)号：US06555396B1

    公开(公告)日：2003-04-29

    申请号：US10097159

    申请日：2002-03-13

    申请人： Ailian Zhao ,  John A. Iacoponi ,  Thomas E. Spikes, Jr.

    发明人： Ailian Zhao ,  John A. Iacoponi ,  Thomas E. Spikes, Jr.

    IPC分类号： H01L2100

    CPC分类号： H01L21/31116

    摘要： A method is provided to enhance endpoint detection during via etching in the processing of a semiconductor wafer. The method includes forming a first process layer and a second process layer above the first process layer. A first masking layer is formed above at least a portion of the second process layer, leaving an outer edge portion of at least the second process layer exposed. Thereafter, an etching process is used to remove the outer edge portion of the first and second layers. Once the etching is complete, the first masking layer is removed, and a second masking layer is formed above the second process layer. The second masking layer is patterned to expose portions of the first process layer, and then an etching process substantially removes the exposed portions of the first process layer to form the vias.

    摘要翻译： 提供了一种在半导体晶片的处理中增强通孔蚀刻期间的端点检测的方法。 该方法包括在第一处理层上形成第一处理层和第二处理层。 第一掩模层形成在第二工艺层的至少一部分之上，留下至少第二工艺层的外边缘部分露出。 此后，使用蚀刻工艺去除第一和第二层的外边缘部分。 蚀刻完成后，去除第一掩模层，并在第二工艺层上方形成第二掩模层。 图案化第二掩模层以暴露第一工艺层的部分，然后蚀刻工艺基本上去除第一工艺层的暴露部分以形成通路。

    Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application
    7.
    发明授权
    Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application 有权
    将低K SiOF作为层间电介质的集成应用于AL间隙填充

    公开(公告)号：US6166427A

    公开(公告)日：2000-12-26

    申请号：US231649

    申请日：1998-01-15

    申请人： Richard J. Huang ,  John A. Iacoponi

    发明人： Richard J. Huang ,  John A. Iacoponi

    IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L23/58 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02131 ,  C23C16/401 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/02362 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for producing a dielectric layer in a semiconductor product includes two steps. The first step is forming a fluorinated layer (e.g. SiOF or fluorosilicate glass ("FSG")) which includes a material formed in part with fluorine. The second step is forming a fill layer (e.g. SiO.sub.2) above the fluorinated layer. The fill layer is substantially free of materials formed in part with fluorine. A top surface of the fill layer can be planarized. Surface treatments and oxide caps can be applied to the planarized surface to form fluorine barriers if part of the fluorinated layer is exposed to higher layers. Such a method, and a semiconductor device or integrated circuit manufactured according to the method, allow the dielectric constant of an inter-layer dielectric ("ILD") to be lowered while also minimizing the complexity and expense of the manufacturing process.

    摘要翻译： 半导体产品中的介电层的制造方法包括两个步骤。 第一步是形成氟化层（例如SiOF或氟硅酸盐玻璃（“FSG”），其包括部分由氟形成的材料。 第二步是在氟化层之上形成填充层（例如SiO 2）。 填充层基本上不含部分由氟形成的材料。 填充层的顶表面可以被平坦化。 如果氟化层的一部分暴露于较高层，则表面处理和氧化物盖可以施加到平坦化表面以形成氟阻挡层。 这样的方法以及根据该方法制造的半导体器件或集成电路能够降低层间电介质（“ILD”）的介电常数，同时也使制造工艺的复杂性和费用最小化。

    METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE
    9.
    发明申请
    METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS PROFILE 有权
    用于形成具有连续记录轮廓的集成电路的方法

    公开(公告)号：US20130309868A1

    公开(公告)日：2013-11-21

    申请号：US13476860

    申请日：2012-05-21

    申请人： Xiuyu Cai ,  Xunyuan Zhang ,  Ruilong Xie ,  Errol T. Ryan ,  John A. Iacoponi

    发明人： Xiuyu Cai ,  Xunyuan Zhang ,  Ruilong Xie ,  Errol T. Ryan ,  John A. Iacoponi

    IPC分类号： H01L21/311

    CPC分类号： H01L21/311 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76831 ,  H01L29/66545

    摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.

    摘要翻译： 为形成集成电路提供了方法。 在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。 侧壁间隔件形成在牺牲心轴的相邻侧壁处。 侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。 侧壁间隔物还具有与基底基板间隔开的上部。 上部具有倾斜的外表面。 第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。 在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。 凹槽的重新设计简洁直观。