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    Nonvolatile semiconductor memory device
    21.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US06324100B1

    公开(公告)日：2001-11-27

    申请号：US09708471

    申请日：2000-11-09

    申请人： Shigeru Atsumi ,  Sumio Tanaka

    发明人： Shigeru Atsumi ,  Sumio Tanaka

    IPC分类号： G11C1606

    CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

    摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

    摘要翻译： 在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。 外围晶体管TR形成在N型阱中。 另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。 基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。 通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。

    Nonvolatile semiconductor memory device
    24.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4879689A

    公开(公告)日：1989-11-07

    申请号：US30065

    申请日：1987-03-25

    申请人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobauki Otsuka

    发明人： Shigeru Atsumi ,  Sumio Tanaka ,  Shinji Saito ,  Nobauki Otsuka

    IPC分类号： G11C17/00 ,  G11C16/08 ,  G11C16/22 ,  G11C16/32 ,  G11C29/00 ,  G11C29/46 ,  G11C29/52 ,  G11C29/56

    CPC分类号： G11C29/52 ,  G11C16/08 ,  G11C16/225 ,  G11C16/32 ,  G11C29/46

    摘要： A nonvolatile semiconductor memory device comprising a matrix array of memory cells, word lines for driving the rows of memory cells, bit lines for reading data from columns of memory cells, a plurality of first MOS transistors provided for these bit lines, respectively, a second MOS transistor having a source coupled to the bit lines by the first MOS transistors, a drain coupled to a VCC terminal, and a gate connected to receive a predetermined bias voltage, a row decoder for selecting one of the word lines in accordance with a row-address signal, and a column decoder for turning on one of the first MOS transistors in accordance with a column-address signal. The memory device further has a CE terminal for receiving a test-mode signal, an OE terminal for receiving first and second control signals, and a control circuit for detecting a test mode, thereby prohibiting the operation of the row decoder in response to the first control signal, and permitting the operation of the row decoder in response to the second control signal.

    摘要翻译： 一种非易失性半导体存储器件，包括存储单元的矩阵阵列，用于驱动存储单元行的字线，用于从存储单元的列读取数据的位线，分别为这些位线提供的多个第一MOS晶体管，第二 MOS晶体管，其具有通过第一MOS晶体管耦合到位线的源极，耦合到VCC端子的漏极和连接以接收预定偏置电压的栅极;行解码器，用于根据行选择字线之一 地址信号，以及列解码器，用于根据列地址信号接通第一MOS晶体管中的一个。 存储装置还具有用于接收测试模式信号的＆amp; amp＆amp;＆amp; C端子，用于接收第一和第二控制信号的＆amp; upbar＆O端子，以及用于检测测试模式的控制电路，从而阻止行解码器响应于 第一控制信号，并且响应于第二控制信号允许行解码器的操作。

    Nonvolatile semiconductor memory device
    25.
    发明授权
    Nonvolatile semiconductor memory device 有权
    与堆叠栅极电池一起使用的非易失性半导体存储器件

    公开(公告)号：US6151252A

    公开(公告)日：2000-11-21

    申请号：US468316

    申请日：1999-12-21

    申请人： Shigeru Atsumi ,  Sumio Tanaka

    发明人： Shigeru Atsumi ,  Sumio Tanaka

    IPC分类号： H01L21/8247 ,  G11C16/08 ,  G11C16/30 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

    CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

    摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

    摘要翻译： 在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。 外围晶体管TR形成在N型阱中。 另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。 基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。 通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。

    Voltage level converting circuit
    29.
    发明授权
    Voltage level converting circuit 失效
    电压电平转换电路

    公开(公告)号：US4926070A

    公开(公告)日：1990-05-15

    申请号：US291933

    申请日：1988-12-30

    申请人： Sumio Tanaka ,  Shigeru Atsumi

    发明人： Sumio Tanaka ,  Shigeru Atsumi

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/12 ,  H03K5/02 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185

    CPC分类号： G11C16/12 ,  H03K19/00361 ,  H03K19/01721 ,  H03K19/018521

    摘要： A voltage level converting circuit for outputting an output signal of a write voltage level responsive to a read voltage level input signal comprises an inverter circuit biased with a power supply of the first voltage level. The input signal is supplied through a transfer gate circuit. A MOS transistor is provided between the input of the inverter circuit and a power supply of the write voltage level to pull-up the voltage level of the input to the inverter circuit responsive to the output of the inverter circuit. Another MOS transistor is provided between the output of the inverter circuit and ground to pull-down the output voltage level responsive to the input signal.

    摘要翻译： 用于响应于读取电压电平输入信号输出写入电压电平的输出信号的电压电平转换电路包括用第一电压电平的电源偏置的反相器电路。 输入信号通过传输门电路提供。 在逆变器电路的输入端和写入电压电平的电源之间设置MOS晶体管，以响应于反相器电路的输出而将输入的电压电平上拉到逆变器电路。 另一个MOS晶体管设置在反相器电路的输出端和接地端之间，以响应于输入信号下拉输出电压电平。

    Nonvolatile semiconductor memory device
    30.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4912534A

    公开(公告)日：1990-03-27

    申请号：US394278

    申请日：1989-08-14

    申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Kenji Shibata ,  Koichi Kanzaki

    发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Kenji Shibata ,  Koichi Kanzaki

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/7881 ,  G11C16/0441

    摘要： A second impurity diffusion layer is formed in a semiconductor substrate at a fixed distance from a first diffusion layer in the substrate. The diffusion layer is supplied with a program potential. An electrode is placed on the channel region between the first and second diffusion layers. Non-selected memory cells are prevented from becoming half-selected by electrically separating the first diffusion layer from the program potential according to signals from the electrode, resulting in substantial improvements in the reliability of the semiconductor device.

    摘要翻译： 第二杂质扩散层形成在与衬底中的第一扩散层固定距离的半导体衬底中。 向扩散层提供程序电位。 电极放置在第一和第二扩散层之间的沟道区上。 通过根据来自电极的信号将第一扩散层与编程电位进行电分离，防止了未选择的存储单元的半选择，从而显着提高了半导体器件的可靠性。