公开(公告)号：US20050174919A1

公开(公告)日：2005-08-11

申请号：US10905767

申请日：2005-01-20

Applicant: Shih-Chieh Chang ,  Chun-Lin Kuo

Inventor： Shih-Chieh Chang ,  Chun-Lin Kuo

IPC: G02B6/27 ,  G02B27/28 ,  G11B7/00

CPC classification number: G02B27/283 ,  G02B6/2713 ,  G02B6/276 ,  G02B6/278 ,  G02B6/29383

Abstract: A optical polarization controller for receiving an input light beam and outputting a transverse magnetic (TM) polarized light beam or transverse electric (TE) polarized light beam is provided. The optical polarization controller includes a polarization splitting device and a half-wave plate. The polarization splitting device is provided for receiving the input light beam and outputting a first light beam and a second light beam. In addition, the half-wave plate is switchably disposed in the light path of the first light beam or the second light beam.

Abstract translation: 提供一种用于接收输入光束并输出横向磁（TM）偏振光束或横向电（TE）偏振光束的光偏振控制器。 光偏振控制器包括偏振分离装置和半波片。 偏振分束装置用于接收输入光束并输出第一光束和第二光束。 此外，半波片可切换地设置在第一光束或第二光束的光路中。

公开(公告)号：US08891299B2

公开(公告)日：2014-11-18

申请号：US13571153

申请日：2012-08-09

Applicant: Ting-Chang Chang ,  Chih-Hao Dai ,  Fu-Yen Jian ,  Wen-Hung Lo ,  Shih-Chieh Chang ,  Ying-Lang Wang

Inventor： Ting-Chang Chang ,  Chih-Hao Dai ,  Fu-Yen Jian ,  Wen-Hung Lo ,  Shih-Chieh Chang ,  Ying-Lang Wang

IPC: G11C11/34 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/7887 ,  H01L29/7923

Abstract: A method for performing a programming operation to a first memory bit and a second memory bit of a device is described. The method includes applying a pulse train voltage to a metal gate of the device and grounding a substrate of the device. By floating/grounding a drain of the device and/or by floating/grounding the source of the device, the first memory and the second memory bit are programmed. The pulse train voltage includes 10 to 1000 pulses. One pulse includes a peak voltage and a base voltage. The peak voltage ranges from 0.5 V to 10 V. A duration of the peak voltage ranges from 1 nanosecond to 1 millisecond. The base voltage is 0 V. A duration of the base voltage ranges from 1 nanosecond to 1 millisecond.

Abstract translation: 描述了用于对设备的第一存储器位和第二存储器位执行编程操作的方法。 该方法包括将脉冲串电压施加到该器件的金属栅极并将器件的衬底接地。 通过浮置/接地设备的漏极和/或通过浮置/接地设备的源，第一存储器和第二存储器位被编程。 脉冲串电压包括10到1000个脉冲。 一个脉冲包括峰值电压和基极电压。 峰值电压范围为0.5V至10V。峰值电压的持续时间范围为1纳秒至1毫秒。 基极电压为0V。基极电压的持续时间范围为1纳秒至1毫秒。

公开(公告)号：US20140043899A1

公开(公告)日：2014-02-13

申请号：US13571153

申请日：2012-08-09

Applicant: Ting-Chang Chang ,  Chih-Hao Dai ,  Fu-Yen Jian ,  Wen-Hung Lo ,  Shih-Chieh Chang ,  Ying-Lang Wang

Inventor： Ting-Chang Chang ,  Chih-Hao Dai ,  Fu-Yen Jian ,  Wen-Hung Lo ,  Shih-Chieh Chang ,  Ying-Lang Wang

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/7887 ,  H01L29/7923

Abstract: A method for performing a programming operation to a first memory bit and a second memory bit of a device is described. The method includes applying a pulse train voltage to a metal gate of the device and grounding a substrate of the device. By floating/grounding a drain of the device and/or by floating/grounding the source of the device, the first memory and the second memory bit are programmed. The pulse train voltage includes 10 to 1000 pulses. One pulse includes a peak voltage and a base voltage. The peak voltage ranges from 0.5 V to 10 V. A duration of the peak voltage ranges from 1 nanosecond to 1 millisecond. The base voltage is 0 V. A duration of the base voltage ranges from 1 nanosecond to 1 millisecond.

Abstract translation: 描述了用于对设备的第一存储器位和第二存储器位执行编程操作的方法。 该方法包括将脉冲串电压施加到该器件的金属栅极并将器件的衬底接地。 通过浮置/接地设备的漏极和/或通过浮置/接地设备的源，第一存储器和第二存储器位被编程。 脉冲串电压包括10到1000个脉冲。 一个脉冲包括峰值电压和基极电压。 峰值电压范围为0.5V至10V。峰值电压的持续时间范围为1纳秒至1毫秒。 基极电压为0V。基极电压的持续时间范围为1纳秒至1毫秒。

公开(公告)号：US08531036B2

公开(公告)日：2013-09-10

申请号：US13563495

申请日：2012-07-31

Applicant: Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

Inventor： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

IPC: H01L23/48

CPC classification number: H01L21/76831 ,  H01L21/7684

Abstract: A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.

Abstract translation: 提供半导体结构，并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。

公开(公告)号：US20120292768A1

公开(公告)日：2012-11-22

申请号：US13563495

申请日：2012-07-31

Applicant: Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

Inventor： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Jung-Chih Tsao ,  Yu-Sheng Wang

IPC: H01L23/52

CPC classification number: H01L21/76831 ,  H01L21/7684

Abstract: A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.

Abstract translation: 提供半导体结构，并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。

公开(公告)号：US07828109B2

公开(公告)日：2010-11-09

申请号：US12467410

申请日：2009-05-18

Applicant: Shih-Chieh Chang

Inventor： Shih-Chieh Chang

IPC: B62D7/00

CPC classification number: B62D1/22 ,  B62D7/14 ,  B62D7/1518 ,  B62D7/1581 ,  B62D7/159

Abstract: The present invention discloses a transmission and steering system of a double-head vehicle, comprising a first steering wheel; a front wheel group; a first signal acquisition and transceiver device which can output steering information according to the steering angle of the first steering wheel; a first motor group; a second signal acquisition and transceiver device which can receive the steering information output from the first signal acquisition and transceiver device; a rear wheel group; and a second motor group; such that through the aforementioned structure, when the first steering wheel is turned, the first motor group may be controlled by the first steering wheel to drive the front wheel group to turn and in the mean time, the second signal acquisition and transceiver device may receive the steering information and transmit it to the second motor group to drive the rear wheel group.

Abstract translation: 本发明公开了一种双头车辆的变速器和转向系统，包括第一方向盘; 前轮组; 第一信号采集和收发器装置，其可以根据第一方向盘的转向角输出转向信息; 第一动力组; 第二信号采集和收发器装置，其可以接收从第一信号采集和收发器装置输出的转向信息; 后轮组; 和第二马达组; 使得通过上述结构，当第一方向盘转动时，可以由第一方向盘控制第一电动机组以驱动前轮组转动，并且同时第二信号采集和收发器装置可以接收 转向信息并将其发送到第二电动机组以驱动后轮组。

公开(公告)号：US07350094B2

公开(公告)日：2008-03-25

申请号：US10942891

申请日：2004-09-17

Applicant: Wen-Fu Tsai ,  Chien-Chih Lin ,  Shih-Chieh Chang

Inventor： Wen-Fu Tsai ,  Chien-Chih Lin ,  Shih-Chieh Chang

IPC: G06F1/00

CPC classification number: G06F13/4278

Abstract: An ultrawideband (UWB) frequency-tracking method and related device are provided. The method includes the following steps: (a) using an initial frequency seed to automatically track and compensate the clock signal of the USB peripheral device; (b) determining whether the automatic tracking and compensating of the clock signal is successful, for example, within a pre-defined duration; (c) if not successful in step (b), setting a new frequency seed; (d) setting the USB peripheral device off-line; and (e) reconnecting the USB peripheral device and using the new frequency seed to perform the tracking and compensating of the clock signal. The setting off-line step is to disable the pull-up resistor of the D+ signal or the pull-up resistor of the D− signal of the USB peripheral device so that the USB peripheral device becomes off-line.

Abstract translation: 提供超宽带（UWB）频率跟踪方法及相关设备。 该方法包括以下步骤：（a）使用初始频率种子来自动跟踪和补偿USB外围设备的时钟信号; （b）确定时钟信号的自动跟踪和补偿是否成功，例如在预定义的持续时间内; （c）如果在步骤（b）中不成功，则设置新的频率种子; （d）脱机设定USB外围设备; 和（e）重新连接USB外围设备并使用新的频率种子来执行对时钟信号的跟踪和补偿。 设置离线步骤是禁用USB外围设备的D信号或D-信号的上拉电阻的上拉电阻，以使USB外围设备脱机。

公开(公告)号：US20070257366A1

公开(公告)日：2007-11-08

申请号：US11416945

申请日：2006-05-03

Applicant: Yu-Sheng Wang ,  Jung-Chih Tsao ,  Kei-Wei Chen ,  Shih-Chieh Chang ,  Ying-Lang Wang

Inventor： Yu-Sheng Wang ,  Jung-Chih Tsao ,  Kei-Wei Chen ,  Shih-Chieh Chang ,  Ying-Lang Wang

IPC: H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/76844 ,  H01L21/76865

Abstract: A method for producing a semiconductor-device having an electrical interconnect. The method produces having an improved barrier layer between the interconnect conductor and the dielectric material in which the interconnect recess is formed. A dielectric layer is formed on top of a wafer substrate having at least one contact region. An interconnect for servicing the contact region is fabricated by forming an interconnect recess and then depositing a primary barrier layer of tantalum nitride and subjecting it to a re-sputtering operation. A film layer of tantalum is then deposited and re-sputtered. Following this operation, a seed layer is formed, and then a conductor is used to fill the interconnect recess. Planerizing the surface of the wafer so that further fabrication may be performed may complete the process.

Abstract translation: 一种具有电互连的半导体器件的制造方法。 该方法产生在互连导体和形成有互连凹槽的电介质材料之间具有改进的阻挡层。 在具有至少一个接触区域的晶片衬底的顶部上形成电介质层。 通过形成互连凹槽然后沉积氮化钽的主阻挡层并对其进行再溅射操作来制造用于维护接触区域的互连。 然后沉积钽薄膜层并重新溅射。 在该操作之后，形成种子层，然后使用导体来填充互连凹槽。 使晶片的表面平整化，以便进一步制造可以完成该工艺。

公开(公告)号：US20060086609A1

公开(公告)日：2006-04-27

申请号：US10971836

申请日：2004-10-22

Applicant: Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

Inventor： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

IPC: C25B11/02

CPC classification number: H01L21/2885 ,  C25D17/001 ,  C25D17/12 ,  Y10T29/49208 ,  Y10T29/53204

Abstract: A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.

Abstract translation: 公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。 电流调平电极包括基极和由基极承载的至少一个子电极。 所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

公开(公告)号：US4555088A

公开(公告)日：1985-11-26

申请号：US653487

申请日：1984-09-24

Applicant: Shih-Chieh Chang

Inventor： Shih-Chieh Chang

IPC: E04G9/05 ,  E04G9/10 ,  E04G17/02 ,  B28B7/28

CPC classification number: E04G17/02 ,  E04G9/05 ,  E04G9/10

Abstract: A reusable panel system for making concrete form structures, especially, after concrete is hardened, forms are dismantled and construction is finished, various patterns or designs will be left on the ceiling and beam, and these patterns or designs are uniform, smooth and delicate, therefore, they could save labor and material and make building have a nice appearance.

Abstract translation: 一种用于制造混凝土结构的可重复使用的面板系统，特别是在混凝土硬化后，形式被拆除，结构完成，各种图案或设计将留在天花板和梁上，这些图案或设计均匀，光滑细腻， 因此，它们可以节省人力和物力，使建筑物的外观美观。