公开(公告)号：US09257501B2

公开(公告)日：2016-02-09

申请号：US14138270

申请日：2013-12-23

申请人： Hidefumi Takaya ,  Masaru Nagao ,  Narumasa Soejima

发明人： Hidefumi Takaya ,  Masaru Nagao ,  Narumasa Soejima

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/739

CPC分类号： H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611

摘要： A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure.

摘要翻译： 半导体器件的半导体衬底包括形成在元件区域中的第一导电体区域; 形成在所述元件区域中的第二导电漂移区; 栅电极，其形成在元件区域中，其布置在栅沟槽中并且面向所述主体区域; 绝缘体，其形成在所述元件区域中并且布置在所述栅电极和所述栅沟槽的内壁之间; 第一导电浮动区域，其形成在所述元件区域中并且被所述漂移区域包围; 第一耐电压保持结构，其形成在所述周边区域中并且围绕所述元件区域; 以及形成在周边区域中的栅极焊盘，并且在第一耐压保持结构的元件区域侧的位置与电极电连接。

公开(公告)号：US20140183620A1

公开(公告)日：2014-07-03

申请号：US14138270

申请日：2013-12-23

申请人： Hidefumi Takaya ,  Masaru Nagao ,  Narumasa Soejima

发明人： Hidefumi Takaya ,  Masaru Nagao ,  Narumasa Soejima

IPC分类号： H01L29/78 ,  H01L29/16

CPC分类号： H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611

摘要： A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure.

摘要翻译： 半导体器件的半导体衬底包括形成在元件区域中的第一导电体区域; 形成在所述元件区域中的第二导电漂移区; 栅电极，其形成在元件区域中，其布置在栅沟槽中并且面向所述主体区域; 绝缘体，其形成在所述元件区域中并且布置在所述栅电极和所述栅沟槽的内壁之间; 第一导电浮动区域，其形成在所述元件区域中并且被所述漂移区域包围; 第一耐电压保持结构，其形成在所述周边区域中并且围绕所述元件区域; 以及形成在周边区域中的栅极焊盘，并且在第一耐压保持结构的元件区域侧的位置与电极电连接。

公开(公告)号：US08440524B2

公开(公告)日：2013-05-14

申请号：US13030790

申请日：2011-02-18

申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Jun Kawai ,  Takeo Yamamoto ,  Takeshi Endo ,  Takashi Katsuno ,  Yukihiko Watanabe ,  Narumasa Soejima

发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Jun Kawai ,  Takeo Yamamoto ,  Takeshi Endo ,  Takashi Katsuno ,  Yukihiko Watanabe ,  Narumasa Soejima

IPC分类号： H01L21/00

CPC分类号： H01L29/7811 ,  C21D1/09 ,  C22F1/10 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/268 ,  H01L21/324 ,  H01L21/67115 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/872

摘要： A method for manufacturing a semiconductor device including a semiconductor substrate composed of silicon carbide, an upper surface electrode which contacts an upper surface of the substrate, and a lower surface electrode which contacts a lower surface of the substrate, the method including steps of: (a) forming an upper surface structure on the upper surface side of the substrate, and (b) forming a lower surface structure on the lower surface side of the substrate. The step (a) comprises steps of: (a1) depositing an upper surface electrode material layer on the upper surface of the substrate, the upper surface electrode material layer being a raw material layer of the upper surface electrode, and (a2) annealing the upper surface electrode material layer. The step (b) comprises steps of: (b1) depositing a lower surface electrode material layer on the lower surface of the substrate, the lower surface electrode material layer being a raw material layer of the lower surface electrode, and (b2) annealing the lower surface electrode material layer with a laser to make an ohmic contact between the lower surface electrode and the substrate.

摘要翻译： 一种半导体器件的制造方法，该半导体器件包括由碳化硅构成的半导体衬底，与衬底的上表面接触的上表面电极和与衬底的下表面接触的下表面电极，该方法包括以下步骤：（ a）在基板的上表面侧上形成上表面结构，（b）在基板的下表面侧形成下表面结构。 步骤（a）包括以下步骤：（a1）在基板的上表面上沉积上表面电极材料层，上表面电极材料层是上表面电极的原料层，（a2）使 上表面电极材料层。 步骤（b）包括以下步骤：（b1）在基板的下表面上沉积下表面电极材料层，下表面电极材料层是下表面电极的原料层，（b2）使 下表面电极材料层用激光器在下表面电极和衬底之间形成欧姆接触。

公开(公告)号：US08748975B2

公开(公告)日：2014-06-10

申请号：US13712343

申请日：2012-12-12

申请人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

发明人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/26506 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

摘要： A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region.

摘要翻译： 提供了具有半导体衬底的开关元件。 沟槽栅电极形成在半导体衬底的上表面中。 在与半导体衬底中的栅极绝缘膜接触的区域中形成n型第一半导体区域，p型第二半导体区域和n型第三半导体区域。 在第二半导体区域下方的位置处，形成连接到第二半导体区域的p型第四半导体区域，并且经由第三半导体区域与栅极绝缘膜相对并且含有硼。 在第三半导体区域的至少一部分中，形成具有比在半导体衬底的下表面露出的半导体区域更高的碳浓度的高浓度含碳区域，位于第四半导体区域 以及与第四半导体区域接触的栅极绝缘膜。

公开(公告)号：US20090134456A1

公开(公告)日：2009-05-28

申请号：US11921085

申请日：2006-05-25

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/207 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7828 ,  H01L29/7832

摘要： The present invention aims to suppress the diffusion of p-type impurities (typically magnesium), included in a semiconductor region of a III-V compound semiconductor, into an adjoining different semiconductor region. A semiconductor device 10 of the present invention comprises a first semiconductor region 28 of gallium nitride (GaN) including p-type impurities that consist of magnesium, a second semiconductor region 34 of gallium nitride, and an impurity diffusion suppression layer 32 of silicon oxide (SiO2) located between the first semiconductor region 28 and the second semiconductor region 34.

摘要翻译： 本发明旨在抑制包含在III-V族化合物半导体的半导体区域中的p型杂质（通常为镁）扩散到邻接的不同半导体区域中。 本发明的半导体器件10包括由镁构成的p型杂质，氮化镓的第二半导体区域34和氧化硅的杂质扩散抑制层32的氮化镓（GaN）的第一半导体区域28（ SiO 2），位于第一半导体区域28和第二半导体区域34之间。

公开(公告)号：US07777252B2

公开(公告)日：2010-08-17

申请号：US11632665

申请日：2005-06-22

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/739 ,  H01L31/072

CPC分类号： H01L29/778 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

摘要翻译： 半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。 此外，SI-GaN层的杂质浓度小于1×1017cm-3。 包括III-V半导体的半导体器件可以具有稳定的常关断操作。

公开(公告)号：US08008749B2

公开(公告)日：2011-08-30

申请号：US11667735

申请日：2005-11-14

申请人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

发明人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

IPC分类号： H01L29/20

CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/41 ,  H01L29/778 ,  H01L29/7788 ,  H01L29/8122

摘要： A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

摘要翻译： 半导体器件设置有漏电极22，半导体基板32，覆盖半导体基板32的一部分表面的电流调节层42，并在半导体基板的表面留下未被覆盖的表面55 板32，覆盖电流调节层42的表面的半导体层50和形成在半导体层50的表面的源电极62.漂移区56，沟道形成区54和源极区52是 形成在半导体层50内。漏电极22连接到电源的第一端子，源电极62连接到电源的第二端子。 利用该半导体层50，可以提高耐压或减少电流泄漏的发生。

公开(公告)号：US07800130B2

公开(公告)日：2010-09-21

申请号：US11795117

申请日：2006-01-20

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/778

CPC分类号： H01L29/452 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.

摘要翻译： 半导体器件10包括由p型氮化镓制成的下半导体层26和由n型AlGaN制成的上半导体层28之间的异质结，其中上半导体层28具有比下半导体层26更大的带隙 半导体器件10还包括形成在上半导体层28的顶表面的一部分上的漏极32，形成在上半导体层28的顶表面的不同部分上的源极34和栅电极 36电连接到下半导体层26.半导体器件10可以正常工作。

公开(公告)号：US20080073652A1

公开(公告)日：2008-03-27

申请号：US11632665

申请日：2005-06-22

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/205 ,  H01L21/338 ,  H01L29/778

CPC分类号： H01L29/778 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： The semiconductor device has a stacked structure in which a p-GaN layer 32, an SI-GaN layer 62, and an AlGaN layer 34 are stacked, and has a gate electrode 44 that is formed at a top surface side of the AlGaN layer 34. A band gap of the AlGaN layer 34 is wider than a band gap of the p-GaN layer 32 and the SI-GaN layer 62. Moreover, impurity concentration of the SI-GaN layer 62 is less than 1×1017 cm−3. The semiconductor devices comprising III-V semiconductors that have a stable normally-off operation are realized.

摘要翻译： 半导体器件具有层叠p-GaN层32，SI-GaN层62和AlGaN层34的堆叠结构，并且具有形成在AlGaN层34的顶面侧的栅电极44 AlGaN层34的带隙比p-GaN层32和SI-GaN层62的带隙宽。另外，SI-GaN层62的杂质浓度小于1×10 17 / SUP> cm 3 -3。 实现了具有稳定的常关断操作的包括III-V半导体的半导体器件。

公开(公告)号：US09184271B2

公开(公告)日：2015-11-10

申请号：US12822328

申请日：2010-06-24

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L21/28 ,  H01L29/20

CPC分类号： H01L29/778 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

摘要翻译： 半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。 此外，SI-GaN层的杂质浓度小于1×1017cm-3。 包括III-V半导体的半导体器件可以具有稳定的常关断操作。