公开(公告)号：US10089174B2

公开(公告)日：2018-10-02

申请号：US15232814

申请日：2016-08-10

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G06F3/06 ,  G11C16/26 ,  G11C11/56 ,  G11C29/52 ,  G11C7/10 ,  G11C16/10 ,  G11C16/04

Abstract: A method for accessing a flash memory module includes: sequentially writing Nth-(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth-(N+K)th data to generate Nth-(N+K)th ECCs, respectively, where the Nth-(N+K)th ECCs are used to correct errors of the Nth-(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth-(N+K)th ECCs to generate the (N+K+1)th ECC.

公开(公告)号：US20180260322A1

公开(公告)日：2018-09-13

申请号：US15979467

申请日：2018-05-15

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G06F12/02 ,  G06F11/10 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C11/56 ,  G11C7/10 ,  G11C29/52 ,  G11C16/04

CPC classification number: G11C29/42 ,  G06F3/0679 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.

公开(公告)号：US20180239670A1

公开(公告)日：2018-08-23

申请号：US15948586

申请日：2018-04-09

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/02

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, is disclosed to include at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

公开(公告)号：US20180122483A1

公开(公告)日：2018-05-03

申请号：US15852847

申请日：2017-12-22

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/3431

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

公开(公告)号：US09959165B2

公开(公告)日：2018-05-01

申请号：US15423593

申请日：2017-02-03

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  H03M13/11 ,  G11C11/56 ,  G11C29/52 ,  G11C16/26

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1102

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

公开(公告)号：US20170317693A1

公开(公告)日：2017-11-02

申请号：US15495992

申请日：2017-04-25

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: H03M13/09 ,  G11C16/26 ,  G11C16/10 ,  H03M13/00 ,  G06F11/10

CPC classification number: H03M13/098 ,  G06F11/1072 ,  G06F11/108 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5641 ,  H03M13/611

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

公开(公告)号：US20170315867A1

公开(公告)日：2017-11-02

申请号：US15495993

申请日：2017-04-25

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/16 ,  G11C11/56 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1072 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0688 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.

公开(公告)号：US20170308318A1

公开(公告)日：2017-10-26

申请号：US15643501

申请日：2017-07-07

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US09627085B2

公开(公告)日：2017-04-18

申请号：US13967371

申请日：2013-08-15

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/34 ,  G11C29/00 ,  G11C11/56

CPC classification number: G11C16/3431 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/34 ,  G11C16/3495 ,  G11C29/00

Abstract: A refresh method for a flash memory includes at least the following steps: performing a write operation to store an input data into a storage space in the flash memory; checking reliability of the storage space with the input data already stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data into the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space into original storage locations in the storage space.

公开(公告)号：US09627050B2

公开(公告)日：2017-04-18

申请号：US15213419

申请日：2016-07-19

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hsiao-Te Chang ,  Wen-Long Wang

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/26 ,  G06F3/06 ,  G11C16/08

CPC classification number: G11C11/5642 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/26

Abstract: A memory access module for performing memory access management of a storage device including a plurality of storage cells includes: sensing means for performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages in order to generate at least a first digital value of a storage cell, wherein each subsequent sensing operation corresponds to a sensing voltage which is determined according to a result of the previous sensing operation; processing means for using the first digital value to obtain soft information of a bit stored in the storage cell; and decoding means for using the soft information to perform soft decoding.