公开(公告)号：US10755779B2

公开(公告)日：2020-08-25

申请号：US15701071

申请日：2017-09-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C7/06

Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.

公开(公告)号：US20200013883A1

公开(公告)日：2020-01-09

申请号：US16576389

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L21/3213 ,  H01L27/11521 ,  H01L27/11536 ,  H01L27/11531 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20200013789A1

公开(公告)日：2020-01-09

申请号：US16578104

申请日：2019-09-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US20190326305A1

公开(公告)日：2019-10-24

申请号：US15957615

申请日：2018-04-19

Applicant: Silicon Storage Technology, Inc.

Inventor： FENG ZHOU ,  Jinho Kim ,  Xian Liu ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/66

Abstract: A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.

公开(公告)号：US20190214397A1

公开(公告)日：2019-07-11

申请号：US16208072

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo Xing ,  Andy Liu ,  Xian Liu ,  Chunming Wang ,  Melvin Dao ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L23/53295 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/42336

Abstract: A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word line gates disposed over and insulated from a portion of the upper surface that is adjacent to the first and second floating gates respectively. A source region is formed in the substrate laterally between the first and second floating gates. First and second channel regions extend from the source region, under the first and second trenches respectively, along side walls of the first and second trenches respectively, and along portions of the upper surface disposed under the first and second word line gates respectively. The first and second trenches only contain the first and second floating gates and insulation material respectively.

公开(公告)号：US10276696B2

公开(公告)日：2019-04-30

申请号：US15494499

申请日：2017-04-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/115 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/423

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US10276236B2

公开(公告)日：2019-04-30

申请号：US15597709

申请日：2017-05-17

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology, and Research

Inventor： Santosh Hariharan ,  Hieu Van Tran ,  Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Nhan Do ,  Zhixian Chen ,  Xinpeng Wang

IPC: G11C13/00 ,  G11C11/00 ,  H01L27/24 ,  H01L45/00

Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.

公开(公告)号：US20180069104A1

公开(公告)日：2018-03-08

申请号：US15474879

申请日：2017-03-30

Applicant: Silicon Storage Technology Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66825 ,  G11C2216/10 ,  H01L21/28273 ,  H01L27/0705 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/788

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US09601500B2

公开(公告)日：2017-03-21

申请号：US14639063

申请日：2015-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

公开(公告)号：US20160379941A1

公开(公告)日：2016-12-29

申请号：US15258069

申请日：2016-09-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L23/00 ,  H01L29/423 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.