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    Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same
    5.
    发明申请
    Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same 有权
    具有硅金属浮栅的分流门非易失性闪存单元及其制作方法

    公开(公告)号：US20150035040A1

    公开(公告)日：2015-02-05

    申请号：US13958483

    申请日：2013-08-02

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev ,  Chien-Sheng Su

    IPC: H01L29/788 ,  H01L29/66

    CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

    Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

    Abstract translation: 非易失性存储单元包括具有第一和第二间隔开的第二导电类型的第一导电类型的衬底，在它们之间形成沟道区。 选择栅极与与第一区域相邻的沟道区域的第一部分绝缘并布置在其上。 浮动栅极与邻近第二区域的沟道区域的第二部分绝缘并布置在其上。 金属材料形成为与浮动栅极接触。 控制栅极与浮动栅极绝缘并设置在浮动栅极上。 擦除栅极包括与第二区域绝缘并且布置在第二区域上的第一部分，并且与浮动栅极绝缘并横向邻近设置，以及与控制栅极绝缘并横向邻近控制栅极的第二部分，并且部分地延伸越过浮动 门。

    Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell
    6.
    发明申请
    Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell 有权
    用于分离门非易失性存储器单元的自对准源的形成

    公开(公告)号：US20150008451A1

    公开(公告)日：2015-01-08

    申请号：US14319893

    申请日：2014-06-30

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Yueh-Hsin Chen

    IPC: H01L27/115 ,  H01L21/8234

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

    Abstract translation: 一种具有一对导电浮动栅极的存储器件，所述导电浮动栅极具有彼此相对的内侧壁，并且设置在第一导电类型的衬底上并与其绝缘。 一对间隔开的导电控制栅极，每个导电控制栅极设置在浮动栅极中的一个上并与其绝缘，并且每个包括面向彼此的内侧壁。 一对绝缘材料的第一间隔物，沿着控制栅极内侧壁和浮动栅极延伸。 浮动门内侧壁与第一间隔件的侧表面对准。 绝缘材料的一对第二间隔物各自沿着第一间隔件中的一个并且沿着浮动栅极内侧壁中的一个延伸。 形成在衬底中的沟槽，其具有与第二间隔物的侧表面对齐的侧壁。 设置在沟槽中的硅碳。 材料注入到硅碳中，形成具有第二导电类型的第一区域。

    Extended Source-Drain MOS Transistors And Method Of Formation
    7.
    发明申请
    Extended Source-Drain MOS Transistors And Method Of Formation 审中-公开
    扩展源极漏极MOS晶体管和形成方法

    公开(公告)号：US20140084367A1

    公开(公告)日：2014-03-27

    申请号：US13974936

    申请日：2013-08-23

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Mandana Tadayoni ,  Yueh-Hsin Chen

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66492 ,  H01L21/265 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A transistor and method of making same include a substrate, a conductive gate over the substrate and a channel region in the substrate under the conductive gate. First and second insulating spacers are laterally adjacent to first and second sides of the conductive gate. A source region in the substrate is adjacent to but laterally spaced from the first side of the conductive gate and the first spacer, and a drain region in the substrate is adjacent to but laterally spaced apart from the second side of the conductive gate and the second spacer. First and second LD regions are in the substrate and laterally extend between the channel region and the source or drain regions respectively, each with a portion thereof not disposed under the first and second spacers nor under the conductive gate, and each with a dopant concentration less than that of the source or drain regions.

    Abstract translation: 晶体管及其制造方法包括衬底，衬底上的导电栅极和导电栅极下的衬底中的沟道区。 第一和第二绝缘间隔件横向邻近导电栅极的第一和第二侧。 衬底中的源极区域与导电栅极和第一间隔物的第一侧相邻但是横向间隔开，并且衬底中的漏极区域与导电栅极的第二侧相邻但横向间隔开，并且第二 间隔 第一LD区域和第二LD区域分别位于衬底中并分别在沟道区域和源极或漏极区域之间横向延伸，每个区域的一部分没有设置在第一和第二间隔物之下，也不设置在导电栅极之下，并且每个具有掺杂剂浓度 比源区或漏区。

    Non-volatile Split Gate Memory Cells With Integrated High K Metal Control Gates And Method Of Making Same
    8.
    发明申请
    Non-volatile Split Gate Memory Cells With Integrated High K Metal Control Gates And Method Of Making Same 审中-公开

    公开(公告)号：US20190172942A1

    公开(公告)日：2019-06-06

    申请号：US16166342

    申请日：2018-10-22

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Chien-Sheng Su ,  Nhan Do

    IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L27/11521

    Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

    Split gate non-volatile flash memory cell having metal gates
    9.
    发明授权
    Split gate non-volatile flash memory cell having metal gates 有权

    公开(公告)号：US10249631B2

    公开(公告)日：2019-04-02

    申请号：US15945161

    申请日：2018-04-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Feng Zhou ,  Jeng-Wei Yang ,  Hieu Van Tran ,  Nhan Do

    IPC: H01L29/423 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524

    Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

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