公开(公告)号：US20230268262A1

公开(公告)日：2023-08-24

申请号：US17750931

申请日：2022-05-23

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Li-Chu Chang ,  Yuan-Hung Hsu ,  Don-Son Jiang

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L23/49833 ,  H01L25/0655 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/481 ,  H01L24/16

Abstract: A method of manufacturing an electronic package is provided and includes disposing a circuit member and a plurality of electronic elements on opposite sides of a carrier structure having circuit layers respectively, so that any two of the plurality of electronic elements can be electrically connected to each other via the circuit layers and the circuit member, where a vertical projected area of the carrier structure is larger than a vertical projected area of the circuit member, such that the circuit member is free from being protruded from side surfaces of the carrier structure. Therefore, the circuit member replaces a part of circuit layers of the carrier structure to reduce the difficulty of fabricating the circuit layers in the carrier structure.

公开(公告)号：US20220189900A1

公开(公告)日：2022-06-16

申请号：US17171764

申请日：2021-02-09

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chia-Yu Kuo ,  Rui-Feng Tai ,  Yih-Jenn Jiang ,  Don-Son Jiang ,  Chang-Fu Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic package is provided and includes at least one conductor with a relatively large width formed on an electrode pad of an electronic element and in contact with a circuit layer. As such, when the electronic element and the circuit layer deviate in position relative to one another, the circuit layer will be still in contact with the conductor and hence electrically connected to the electronic element.

公开(公告)号：US20220093518A1

公开(公告)日：2022-03-24

申请号：US17108399

申请日：2020-12-01

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Cheng Kai Chang ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L23/538 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.

公开(公告)号：US10115712B2

公开(公告)日：2018-10-30

申请号：US14998114

申请日：2015-12-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Chueh Hu ,  Yueh-Chiung Chang ,  Don-Son Jiang

IPC: H01L25/11 ,  H05K7/02 ,  H01Q3/44

Abstract: An electronic module is provided, which includes a first package and a second package stacked on the first package. The first package has an encapsulant and an electronic element embedded in the encapsulant. The second package has an insulating layer and an antenna structure formed on and extending through the insulating layer. The insulating layer is bonded to the encapsulant with the antenna structure being electrically connected to the electronic element. Since the second package having the antenna structure is stacked on the first package, the invention eliminates the need to increase the area of the first package for mounting the antenna structure and hence allows the electronic module to meet the miniaturization requirement.

公开(公告)号：US20150102484A1

公开(公告)日：2015-04-16

申请号：US14136238

申请日：2013-12-20

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD

Inventor： Chia-Cheng Chen ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Liang-yi Hung ,  Wei-chung Hsiao ,  Yu-cheng Pai ,  Shih-Chao Chiu ,  Don-Son Jiang ,  Yi-Feng Chang ,  Lung-Yuan Wang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/535

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1011 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H05K1/181 ,  H05K1/183 ,  H05K3/284 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging.

Abstract translation: 公开了一种封装结构，其包括：第一基板; 形成在第一基板上并电连接到第一基板并具有空腔的积聚层; 至少电子元件设置在所述空腔中并电连接到所述第一基板; 堆叠构件，其设置在堆积层上以堆叠在第一基板上; 以及形成在堆积层和堆叠构件之间的密封剂。 堆积层有助于实现隔离效应并防止焊料桥接。

公开(公告)号：US12027484B2

公开(公告)日：2024-07-02

申请号：US17369029

申请日：2021-07-07

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Ren Chen ,  Po-Yung Chang ,  Pei-Geng Weng ,  Yuan-Hung Hsu ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/56 ,  H01L23/31 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562

Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.

公开(公告)号：US20230307339A1

公开(公告)日：2023-09-28

申请号：US17748920

申请日：2022-05-19

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Ting-Yang Chou ,  Yih-Jenn Jiang ,  Don-Son Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49838 ,  H01L21/4857 ,  H01L25/105

Abstract: An electronic package is provided, and the manufacturing method of which is to form a plurality of conductive pillars and dispose an electronic element on a first circuit structure, then cover the plurality of conductive pillars and the electronic element with a cladding layer, and then form a second circuit structure on the cladding layer, so that the plurality of conductive pillars are electrically connected to the first circuit structure and the second circuit structure, and the electronic element is electrically connected to the first circuit structure, where a fan-out redistribution layer is configured in the first circuit structure and the second circuit structure, and at least one ground layer is configured in the second circuit structure. Further, the ground layer includes a plurality of sheet bodies arranged in an array, so that at least one slot is disposed between every two adjacent sheet bodies.

公开(公告)号：US20230187382A1

公开(公告)日：2023-06-15

申请号：US18109120

申请日：2023-02-13

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chih-Hsun Hsu ,  Chi-Jen Chen ,  Hsi-Chang Hsu ,  Yuan-Hung Hsu ,  Rui-Feng Tai ,  Don-Son Jiang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L25/0655 ,  H01L23/3157 ,  H01L25/50 ,  H01L21/4853 ,  H01L24/05 ,  H01L21/56 ,  H01L2224/05556 ,  H01L24/16 ,  H01L2224/16227

Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.

公开(公告)号：US20230015721A1

公开(公告)日：2023-01-19

申请号：US17411228

申请日：2021-08-25

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Meng-Huan Chia ,  Yih-Jenn Jiang ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L25/065 ,  H01L25/16 ,  H01L25/00

Abstract: An electronic package is provided, in which a first electronic element and a second electronic element are disposed on a first side of a circuit structure and a second side of the circuit structure, respectively, where a first metal layer is formed between the first side of the circuit structure and the first electronic element, a second metal layer is formed on a surface of the second electronic element, and at least one thermally conductive pillar is disposed on the second side of the circuit structure and extends into the circuit structure to thermally conduct the first metal layer and the second metal layer. Therefore, through the thermally conductive pillar, heat generated during operations of the first electronic element and the second electronic element can be quickly dissipated to an external environment and would not accumulate.

公开(公告)号：US20220181225A1

公开(公告)日：2022-06-09

申请号：US17160720

申请日：2021-01-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Jen Chen ,  Hsi-Chang Hsu ,  Yuan-Hung Hsu ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.