公开(公告)号：US08394684B2

公开(公告)日：2013-03-12

申请号：US12841408

申请日：2010-07-22

申请人： Sivananda K. Kanakasabapathy ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Sivananda K. Kanakasabapathy ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/84

CPC分类号： H01L27/0886 ,  H01L21/82 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785

摘要： Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.

摘要翻译： 公开了一种技术来将外部应力施加到源极/漏极半导体鳍状物侧壁区域上并将其锁定到半导体鳍片上，然后释放侧壁以用于随后的盐化和接触形成。 特别地，本公开提供了一种方法，其中半导体的选定部分经受非晶化离子注入，其相对于在栅极堆叠下面的半导体鳍片的部分使半导体鳍片的选定部分的晶体结构脱落， 用各种衬垫封装。 形成至少一个应力衬垫，然后通过进行应力闭锁退火而发生应力记忆。 在该退火期间，发生错位取向的晶体结构的再结晶。 去除至少一个应力衬垫，然后执行源极/漏极区域中的半导体鳍片的合并。

公开(公告)号：US20120187523A1

公开(公告)日：2012-07-26

申请号：US13011546

申请日：2011-01-21

申请人： Jason E. Cummings ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E. Cummings ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76224 ,  H01L21/02107 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.

摘要翻译： 提供浅沟槽隔离区域，其中空隙形成基本上或完全从其中消除。 浅沟槽隔离减轻半导体衬底的两个有源区域之间的有源短路。 浅沟槽隔离区域包括存在于形成在半导体衬底中的沟槽的侧壁和底壁上的双层衬垫。 本公开的双层衬垫包括从底部到顶部的浅沟槽隔离衬垫，例如半导体氧化物和/或氮化物，以及高k衬里，例如介电常数大于硅的介电材料 氧化物。

公开(公告)号：US20120178236A1

公开(公告)日：2012-07-12

申请号：US13422138

申请日：2012-03-16

申请人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

公开(公告)号：US07704854B2

公开(公告)日：2010-04-27

申请号：US12115690

申请日：2008-05-06

申请人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

发明人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

IPC分类号： H01L21/76

CPC分类号： H01L21/76283

摘要： The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner; and filling the shallow trench with oxide material over the metal or metal alloy.

摘要翻译： 本发明涉及一种方法，包括在至少一个SIO层中蚀刻至少一个浅沟槽; 在SIO层和SIO层的界面处形成电介质衬垫; 在电介质衬垫上的浅沟槽中形成金属或金属合金层; 并在金属或金属合金上用氧化物填充浅沟槽。

公开(公告)号：US20100076785A1

公开(公告)日：2010-03-25

申请号：US12284929

申请日：2008-09-25

申请人： Sanjay Mehta ,  Debashis Neogi

发明人： Sanjay Mehta ,  Debashis Neogi

IPC分类号： G06Q50/00 ,  G06F17/30

CPC分类号： G06Q50/24 ,  G06F19/328 ,  G06N20/00 ,  G06Q50/22 ,  G16H50/20 ,  G16H50/50 ,  Y02A90/22 ,  Y02A90/26

摘要： Systems and methods are provided for predicting rare events, such as hospitalization events. Data related to health and/or healthcare may be compiled from a number of sources and used to construct a predictive model. The predictive model employ Principal Component Analysis (PCA) and Partial Least Squares (PLS). The data may be arranged in a timeline, and formatted in such a way as to provide discrete temporal “batches”. This arrangement may facilitate the PCA and PLS decomposition of the data into predictive models. These models may then be applied to an individual's data, to create a prediction of healthcare related events.

摘要翻译： 提供系统和方法来预测罕见事件，如住院事件。 与健康和/或保健有关的数据可以从许多来源编制并用于构建预测模型。 预测模型采用主成分分析（PCA）和偏最小二乘法（PLS）。 数据可以以时间线布置，并且以提供离散时间“批次”的方式进行格式化。 这种安排可以促进PCA和PLS将数据分解成预测模型。 然后可以将这些模型应用于个人的数据，以创建与医疗相关事件的预测。

公开(公告)号：US20080090402A1

公开(公告)日：2008-04-17

申请号：US11536893

申请日：2006-09-29

申请人： Griselda Bonilla ,  Shyng-Tsong Chen ,  John A. Fitzsimmons ,  Sanjay Mehta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Shyng-Tsong Chen ,  John A. Fitzsimmons ,  Sanjay Mehta ,  Shom Ponoth

IPC分类号： H01L21/44

CPC分类号： H01L21/76825 ,  H01J2237/0812 ,  H01L21/76883

摘要： A method of fabricating and a structure of an integrated circuit (IC) incorporating a porous dielectric layer are disclosed. A metal line is formed in the porous dielectric layer. A gas cluster ion beam process is applied to the porous dielectric layer so that an upper portion of the dielectric layer is densified to be not porous or non-interconnected low porous, while a lower portion of the porous dielectric layer still maintains its ultra-low dielectric constant after the gas cluster ion beam process.

摘要翻译： 公开了一种制造方法和结合有多孔介电层的集成电路（IC）的结构。 在多孔介电层中形成金属线。 将气体簇离子束工艺应用于多孔介电层，使得电介质层的上部被致密化为不是多孔的或不互连的低多孔，而多孔介电层的下部仍保持其超低 气体离子束过程后的介电常数。

公开(公告)号：US20080012142A1

公开(公告)日：2008-01-17

申请号：US11307642

申请日：2006-02-15

申请人： Sanjay Mehta ,  Daniel Edelstein ,  John Fitzsimmons ,  Stephan Grunow ,  Henry Nye ,  David Rath

发明人： Sanjay Mehta ,  Daniel Edelstein ,  John Fitzsimmons ,  Stephan Grunow ,  Henry Nye ,  David Rath

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via “anchors” (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration (“drilling, gouging”) into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.

摘要翻译： 提供了使得能够使用较不积极的衬里工艺的能力，同时产生已知具有期望的高应力迁移和电迁移可靠性的结构。 本发明通过化学方法制造通孔“锚”（互锁和相互穿透的通孔）来规避低k（约3.2以下）电介质的溅射损伤问题。 这允许在阻挡/种子金属化步骤中消除或显着减少用于在下面的线中产生通孔穿透（“钻孔，气刨”）的溅射蚀刻工艺。 本发明实现上述，同时保持可靠的铜填充和装置结构。

公开(公告)号：US20070224824A1

公开(公告)日：2007-09-27

申请号：US11609040

申请日：2006-12-11

申请人： Shyng-Tsong Chen ,  Nancy R. Klymko ,  Anita Madan ,  Sanjay Mehta ,  Steven E. Molis

发明人： Shyng-Tsong Chen ,  Nancy R. Klymko ,  Anita Madan ,  Sanjay Mehta ,  Steven E. Molis

IPC分类号： H01L21/311

CPC分类号： H01L21/3105 ,  H01L21/31155 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76831

摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method of repairing process induced dielectric damage from forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes treating an exposed area of the ILD material to create a carbon-rich area, and metallizing the carbon-rich area. One embodiment includes providing treatment to an exposed sidewall area of the ILD material to create a carbon-rich area by irradiating the exposed area using a gas cluster ion beam (GCIB) generated through a gas including a straight chain or branched, aliphatic or aromatic hydrocarbon, and metallizing the carbon-rich area.

摘要翻译： 当互连结构构建在多孔超低k（ULK）材料上时，沟槽和/或通孔的底部和/或侧壁通常被以下金属化或清洁工艺损坏，这可能适合于较高的介电材料。 本发明的实施例可以提供一种通过在层间电介质（ILD）材料上形成互连结构来修复工艺引起的介电损伤的方法。 该方法包括处理ILD材料的暴露区域以产生富含碳的区域，以及使富含碳的区域金属化。 一个实施例包括通过使用通过包括直链或支链，脂族或芳族烃的气体产生的气体簇离子束（GCIB）照射暴露区域来向ILD材料的暴露的侧壁区域提供处理以产生富碳区域 ，并且富含碳的区域金属化。

公开(公告)号：US20060246245A1

公开(公告)日：2006-11-02

申请号：US10569614

申请日：2004-08-05

申请人： Zhenguo Liu ,  Sanjay Mehta ,  Xiaoyan Huang ,  David Schiraldi

发明人： Zhenguo Liu ,  Sanjay Mehta ,  Xiaoyan Huang ,  David Schiraldi

IPC分类号： B65D1/02

CPC分类号： C08K3/24 ,  B29B2911/1402 ,  B29B2911/14026 ,  B29B2911/14033 ,  B29B2911/1404 ,  B29B2911/14106 ,  B29B2911/14133 ,  B29B2911/1416 ,  B29C49/0005 ,  B29C49/06 ,  B29K2067/00 ,  B65D1/0207 ,  C08G63/6886 ,  C08K5/098 ,  C08K5/42 ,  C08L67/02 ,  C08L77/06 ,  Y10T428/13 ,  Y10T428/1352 ,  Y10T428/139 ,  C08L2666/20

摘要： The present invention comprises a blend of polyester and a partially aromatic polyamide with an ionic compatibilizer and a cobalt salt. This blend can be processed into a container that has both active and passive oxygen barrier and carbon dioxide barrier properties at an improved color and clarity than containers known in the art. The partially aromatic polyamide is preferably meta-xylylene adipamide. The ionic compatibilizer is preferably 5-sodiumsulfoisophthalic acid or 5-zincsulfoisophthalic acid, or their dialkyl esters such as the dimethyl ester (SIM) and glycol ester (SIPEG). The cobalt salt is selected form the class of cobalt acetate, cobalt carbonate, cobalt chloride, cobalt hydroxide, cobalt naphthenate, cobalt oleate, cobalt linoleate, cobalt octoate, cobalt stearate, cobalt nitrate, cobalt phosphate, cobalt sulfate, cobalt (ethylene glycolate), or mixtures of two or more of these. The partially aromatic polyamide is present in a range from about 1 to about 10 wt. % of said composition. The ionic compatibilizer is present in a range from about 0.1 to about 2.0 mol-% of said composition. The cobalt salt is present in a range from about 20 to about 500 ppm of said composition.

摘要翻译： 本发明包括聚酯和部分芳族聚酰胺与离子增容剂和钴盐的共混物。 与现有技术中已知的容器相比，该混合物可以加工成具有主动和被动氧气阻隔性和二氧化碳阻隔性能的容器，其颜色和透明度得到改善。 部分芳族聚酰胺优选为间二甲苯基己二酰胺。 离子增容剂优选为5-钠磺基间苯二甲酸或5-锌磺基间苯二甲酸，或其二烷基酯如二甲酯（SIM）和乙二醇酯（SIPEG）。 钴盐选自乙酸钴，碳酸钴，氯化钴，氢氧化钴，环烷酸钴，油酸钴，亚油酸钴，辛酸钴，硬脂酸钴，硝酸钴，磷酸钴，硫酸钴，钴（乙醇酸）等。 ，或这些中的两种或更多种的混合物。 部分芳族聚酰胺的存在量为约1至约10重量％。 ％的所述组合物。 离子相容剂的存在量为所述组合物的约0.1至约2.0mol％。 钴盐以所述组合物的约20至约500ppm的范围存在。

公开(公告)号：US09209126B2

公开(公告)日：2015-12-08

申请号：US13606788

申请日：2012-09-07

申请人： Qinghuang Lin ,  Sanjay Mehta ,  Hosadurga Shobha

发明人： Qinghuang Lin ,  Sanjay Mehta ,  Hosadurga Shobha

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5222 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.

摘要翻译： 互连结构及其制造方法包括层间电介质层的侧壁部分。 侧壁部分具有小于给定平版印刷技术的最小特征尺寸的宽度，并且当在心轴的垂直表面上共形形成时，宽度由层间电介质层的厚度形成。 侧壁部分形成间隔开的开口。 导电结构填充间隔开的开口并且被侧壁部分分开以形成单个镶嵌结构。