公开(公告)号：US06908227B2

公开(公告)日：2005-06-21

申请号：US10227125

申请日：2002-08-23

申请人： Stefan Rusu ,  Simon M. Tam

发明人： Stefan Rusu ,  Simon M. Tam

IPC分类号： G01K1/02 ,  G01K7/42 ,  G06F1/20 ,  G01K13/00 ,  G06F1/32

CPC分类号： G06F1/206 ,  G01K1/026 ,  G01K7/42 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

摘要： An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.

摘要翻译： 描述了一种用于管理具有多核微处理器的集成电路的温度的装置。 具体来说，热传感器放置在每个微处理器核心的潜在热点。 热管理单元监视热传感器。 如果热传感器识别热点，则热管理单元相应地调整该微处理器核心的工作频率和电压。

公开(公告)号：US06788156B2

公开(公告)日：2004-09-07

申请号：US10456660

申请日：2003-06-06

申请人： Simon M. Tam ,  Stefan Rusu

发明人： Simon M. Tam ,  Stefan Rusu

IPC分类号： H03B2800

CPC分类号： G06F1/324 ,  G06F1/3203 ,  H03L7/06 ,  H03L7/0805 ,  Y02D10/126

摘要： A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

摘要翻译： 一种在处理器中动态地改变时钟频率的方法。 一个实施例的方法包括用来自相位锁定环（PLL）的时钟输出来驱动时钟分配网络。 可调时钟发生器与锁相环锁定。 可调时钟发生器代替时钟分配网络上的PLL。

公开(公告)号：US5581473A

公开(公告)日：1996-12-03

申请号：US605800

申请日：1996-02-23

申请人： Stefan Rusu ,  Stuart A. Taylor ,  Peter C. Tong ,  Gregory Schulte

发明人： Stefan Rusu ,  Stuart A. Taylor ,  Peter C. Tong ,  Gregory Schulte

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  Y10S707/99931

摘要： A repository, a loader, a model generator, a constraint generator, and a number of timing analysis tools, are provided for managing timing requirement specifications and measurements, and generating timing models and constraints of a VLSI circuit. The repository stores the timing specifications and measurements for each pin instances and each flow through arc instances. Timing specifications and measurements are identified by their classes including at least one current specification class and at least one measurement class for one timing analysis tool. Additionally, the repository stores a number of characteristics for each pin instance, the pin compositions of each net, and the hierarchical relationship of the functional block instances. The loader loads the various information into the repository. The timing model generator generates the timing models for the various functional blocks, using the stored information in the repository. The timing constraint generator in cooperation with the timing model generator and at least one timing analysis tool generates the timing constraints for the various functional block instances, using the stored information in the repository, the generated timing models of the functional blocks, and a number of timing analysis scripts.

摘要翻译： 提供存储库，加载器，模型生成器，约束生成器和多个时序分析工具，用于管理定时需求规范和测量，以及生成VLSI电路的定时模型和约束。 存储库存储每个针脚实例的时序规格和测量值，每个流程通过圆弧实例。 定时规范和测量由其类别标识，包括至少一个当前规范类别和至少一个测量类别，用于一个时序分析工具。 另外，存储库存储每个引脚实例的多个特性，每个网络的引脚组成以及功能块实例的分层关系。 加载器将各种信息加载到存储库中。 定时模型生成器使用存储库中存储的信息生成各种功能块的时序模型。 与定时模型发生器和至少一个定时分析工具协作的时序约束生成器使用存储库中存储的信息，生成的功能块的定时模型和多个功能块的时间模型来生成各种功能块实例的时序约束 时序分析脚本。

公开(公告)号：US20090089607A1

公开(公告)日：2009-04-02

申请号：US11906008

申请日：2007-09-29

申请人： Jorge Rodriguez ,  Alon Naveh ,  Gil Schwarzband ,  Hung-Piao Ma ,  Stefan Rusu ,  James G. Hermerding ,  Ishmael F. Santos ,  Joseph T. Dibene, II ,  Edward Stanford

发明人： Jorge Rodriguez ,  Alon Naveh ,  Gil Schwarzband ,  Hung-Piao Ma ,  Stefan Rusu ,  James G. Hermerding ,  Ishmael F. Santos ,  Joseph T. Dibene, II ,  Edward Stanford

IPC分类号： G06F1/26

CPC分类号： G06F1/26

摘要： Systems and method for providing a regulated voltage supply to an integrated circuit. In an embodiment of the invention, a voltage regulator in a system provides an integrated circuit in the system with information related to the voltage regulator providing a supply voltage to the integrated circuit. In another embodiment of the invention, the integrated circuit makes determinations about the operating characteristic of the system using information from the voltage regulator.

摘要翻译： 向集成电路提供稳压电源的系统和方法。 在本发明的一个实施例中，系统中的电压调节器为系统中的集成电路提供与电压调节器相关的信息，以向集成电路提供电源电压。 在本发明的另一实施例中，集成电路使用来自电压调节器的信息来确定系统的工作特性。

公开(公告)号：US06762629B2

公开(公告)日：2004-07-13

申请号：US10206610

申请日：2002-07-26

申请人： Simon M. Tam ,  Stefan Rusu

发明人： Simon M. Tam ,  Stefan Rusu

IPC分类号： H03B1900

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3296 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/18 ,  H03L7/22 ,  Y02D10/126 ,  Y02D10/172

摘要： A method and an apparatus for dynamically varying a clock frequency in a processor to adapt to VCC voltage changes. The method of one embodiment includes sampling a supply voltage at a plurality of locations. The values of said supply voltage are communicated to a clock generator. A clock frequency of a clock signal generated from the clock generator is adjusted in response to an evaluation of the sampled values of the supply voltage.

摘要翻译： 一种用于在处理器中动态地改变时钟频率以适应VCC电压变化的方法和装置。 一个实施例的方法包括对多个位置处的电源电压进行采样。 所述电源电压的值被传送到时钟发生器。 响应于对电源电压的采样值的评估，调整从时钟发生器产生的时钟信号的时钟频率。

公开(公告)号：US06201448B1

公开(公告)日：2001-03-13

申请号：US09473925

申请日：1999-12-28

申请人： Simon M. Tam ,  Stefan Rusu

发明人： Simon M. Tam ,  Stefan Rusu

IPC分类号： H03L706

CPC分类号： H03L7/06 ,  G06F1/10 ,  H03L7/081

摘要： An on-die clock generator. For one aspect of the invention, the on-die clock generator includes a phase-locked loop (PLL) circuit having a first input coupled to receive an external clock signal and an output coupled to provide an on-die clock signal to be used during a normal operating mode of an integrated circuit. The on-die clock generator also includes a local clock generator circuit having an input coupled to receive the on-die clock signal and an output coupled to provide a local PLL feedback clock signal to a second input of the PLL.

摘要翻译： 一个片上时钟发生器。 对于本发明的一个方面，片上时钟发生器包括锁相环（PLL）电路，其具有耦合以接收外部时钟信号的第一输入和耦合以提供待使用的时钟信号的输出 集成电路的正常工作模式。 片上时钟发生器还包括具有耦合以接收片上时钟信号的输入的本地时钟发生器电路，以及耦合以将本地PLL反馈时钟信号提供给PLL的第二输入的输出。

公开(公告)号：US5598348A

公开(公告)日：1997-01-28

申请号：US310936

申请日：1994-09-22

申请人： Stefan Rusu ,  Clayton L. Yee

发明人： Stefan Rusu ,  Clayton L. Yee

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5081

摘要： A method and apparatus to model the power network of a VLSI circuit is described. The method includes the step of extracting the power network associated with a semiconductor circuit layout. A compacted power network is then derived from the power network. The compacted power network includes a compacted primary resistive network to characterize the electrical resistance of the power trunks within the semiconductor circuit layout. The compacted power network also includes a compacted secondary resistive network to characterize the electrical resistance of power straps that deliver power to transistors within the semiconductor circuit layout. The compacted power network constitutes a network of compaction component values that correspond to functional regions in the semiconductor circuit layout. Each of the compaction component values includes an associated set of spacial compaction values that characterize the total resistance of a functional region. The operation of the compacted power network is simulated on a circuit simulation program to identify areas in the compacted power network that do not comply with predetermined power network performance criteria, such as electromigration limits and voltage drop limits. The semiconductor circuit layout is then reconfigured to satisfy the predetermined power network performance criteria.

摘要翻译： 描述了对VLSI电路的电力网络进行建模的方法和装置。 该方法包括提取与半导体电路布局相关联的电力网络的步骤。 然后从电力网获得紧凑的电力网络。 压实的电力网络包括压实的主电阻网络，以表征半导体电路布局内的电力中继线的电阻。 压实的电力网络还包括压实的次级电阻网络，以表征向半导体电路布局内的晶体管供电的电力带的电阻。 压实的电力网络构成对应于半导体电路布局中的功能区域的压实部件值的网络。 每个压实部件值包括表征功能区域的总电阻的相关联的一组空间压实值。 压缩电力网络的操作在电路仿真程序上模拟，以识别压缩电力网络中不符合电力迁移限制和电压下降限制的预定电力网络性能标准的区域。 然后重新配置半导体电路布局以满足预定的电力网络性能标准。

公开(公告)号：US5307286A

公开(公告)日：1994-04-26

申请号：US988468

申请日：1992-12-10

申请人： Stefan Rusu ,  Joseph S. Yang

发明人： Stefan Rusu ,  Joseph S. Yang

IPC分类号： H01L21/82 ,  G01R31/3185 ,  G06F17/50 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H03K19/173

CPC分类号： H01L27/0207 ,  G01R31/318583 ,  G06F17/5068

摘要： A computer integrated circuit arrangement including flip-flop circuits, buffers, and combinatorial circuit elements in which the flip-flop circuits are arranged in rows with buffers which may be connected to drive signals to those flip-flop circuits, the flip-flop circuits having conductors designed to carry global signals arranged to traverse the width of the flip-flop circuits and provide input and output terminals to match input and output terminals of adjacent flip-flop circuits.

摘要翻译： 一种包括触发器电路，缓冲器和组合电路元件的计算机集成电路装置，其中触发器电路以可连接到那些触发器电路的驱动信号的缓冲器排成行，触发器电路具有 导体被设计为承载布置成横穿触发器电路的宽度的全局信号，并提供输入和输出端子以匹配相邻触发器电路的输入和输出端子。

公开(公告)号：US09087146B2

公开(公告)日：2015-07-21

申请号：US13723304

申请日：2012-12-21

申请人： Stefan Rusu ,  Zhiguo Wang ,  Krishnakanth V. Sistla

发明人： Stefan Rusu ,  Zhiguo Wang ,  Krishnakanth V. Sistla

IPC分类号： G06F11/00 ,  G06F11/34

CPC分类号： G06F11/3409 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3058

摘要： Wear-out equalization techniques for multiple functional hardware units are disclosed. An integrated circuit includes a power control unit (PCU) configured to monitor indicators of wear-out incurred by multiple functional hardware units of the integrated circuit. The PCU calculates cumulative wear-out metrics of the functional hardware units based on the monitored indicators and performs an equalization action to equalize the cumulative wear-out metrics of the functional hardware units.

摘要翻译： 公开了用于多个功能硬件单元的磨损均衡技术。 集成电路包括功率控制单元（PCU），其被配置为监视由集成电路的多个功能硬件单元引起的磨损指标。 PCU根据所监视的指示器来计算功能硬件单元的累计磨损量度，并执行均衡动作以均衡功能硬件单元的累积磨损量度。

公开(公告)号：US07464276B2

公开(公告)日：2008-12-09

申请号：US11524220

申请日：2006-09-19

申请人： Stefan Rusu ,  David J. Ayers ,  James S. Burns

发明人： Stefan Rusu ,  David J. Ayers ,  James S. Burns

IPC分类号： G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  G06F1/324 ,  H04B17/10 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for adjusting the voltage and frequency to minimize power dissipation in a processor. The method of one embodiment comprises determining a power consumption value. The power consumption value is evaluated to obtain a new operating point. The new operating point is compared with a present operating point. A frequency setting and a voltage setting are adjusted to correspond to the new operating point if the new operating point is different from the present operating point.

摘要翻译： 一种用于调整电压和频率以最小化处理器功率耗散的方法。 一个实施例的方法包括确定功耗值。 评估功耗值以获得新的工作点。 将新的工作点与现在的工作点进行比较。 如果新的工作点与当前工作点不同，则调整频率设置和电压设置以对应于新的工作点。