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    WEAR-OUT EQUALIZATION TECHNIQUES FOR MULTIPLE FUNCTIONAL UNITS
    8.
    发明申请
    WEAR-OUT EQUALIZATION TECHNIQUES FOR MULTIPLE FUNCTIONAL UNITS 有权
    用于多功能单元的磨损均衡技术

    公开(公告)号：US20140181596A1

    公开(公告)日：2014-06-26

    申请号：US13723304

    申请日：2012-12-21

    申请人： Stefan Rusu ,  Zhiguo Wang ,  Krishnakanth V. Sistla

    发明人： Stefan Rusu ,  Zhiguo Wang ,  Krishnakanth V. Sistla

    IPC分类号： G06F11/34

    CPC分类号： G06F11/3409 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3058

    摘要： Wear-out equalization techniques for multiple functional hardware units are disclosed. An integrated circuit includes a power control unit (PCU) configured to monitor indicators of wear-out incurred by multiple functional hardware units of the integrated circuit. The PCU calculates cumulative wear-out metrics of the functional hardware units based on the monitored indicators and performs an equalization action to equalize the cumulative wear-out metrics of the functional hardware units.

    摘要翻译： 公开了用于多个功能硬件单元的磨损均衡技术。 集成电路包括功率控制单元（PCU），其被配置为监视由集成电路的多个功能硬件单元引起的磨损指标。 PCU根据所监视的指示器来计算功能硬件单元的累计磨损量度，并执行均衡动作以均衡功能硬件单元的累积磨损量度。

    Cache leakage shut-off mechanism
    9.
    发明授权
    Cache leakage shut-off mechanism 有权
    缓存泄漏关闭机制

    公开(公告)号：US07657767B2

    公开(公告)日：2010-02-02

    申请号：US11174204

    申请日：2005-06-30

    申请人： Stefan Rusu ,  Tsung-Yung Chang ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Jonathan Shoemaker ,  Ming Huang

    发明人： Stefan Rusu ,  Tsung-Yung Chang ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Jonathan Shoemaker ,  Ming Huang

    IPC分类号： G06F1/00 ,  G06F1/32

    CPC分类号： G06F1/32 ,  G06F1/3287 ,  G11C11/417 ,  Y02D10/171

    摘要： In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.

    摘要翻译： 在本发明的一个实施例中，提供了一种用于控制高速缓存子阵列的泄漏的技术。 本文公开了其它实施例。 睡眠和关闭电路连接在虚拟供应终端和第一物理供应终端之间，以便在关闭模式下禁用高速缓存子阵列时减少从高速缓存子阵列的泄漏。 高速缓存子阵列连接在虚拟供电终端和第二物理供应终端之间。 有源电路并联连接到睡眠和关闭电路，以使高速缓存子阵列处于正常模式，并在关闭模式下禁用高速缓存子阵列。