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21.发明授权Capacitor structure in trench structures of semiconductor devices and semiconductor devices comprising capacitor structures of this type and methods for fabricating the same 有权包括这种类型的电容器结构的半导体器件和半导体器件的沟槽结构中的电容器结构及其制造方法公开(公告)号：US08187947B2
公开(公告)日：2012-05-29
申请号：US12827035
申请日：2010-06-30
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , H01L27/10861 , H01L28/82
摘要： A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor device.
摘要翻译： 半导体器件的沟槽结构中的电容器结构包括由金属和/或半导体材料制成的导电区域。 导电区域被电介质包围，并在半导体器件的沟槽结构中形成叠层。
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公开(公告)号：US20110147883A1
公开(公告)日：2011-06-23
申请号：US12646503
申请日：2009-12-23
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/0237 , H01L21/02642 , H01L21/02647 , H01L21/31144 , H01L21/74 , H01L21/76224 , H01L21/7624 , H01L21/76248 , H01L21/76283
摘要： Disclosed is a method for forming a buried material layer in a semiconductor body, and a semiconductor arrangement including a buried material layer.
摘要翻译： 公开了一种在半导体本体中形成掩埋材料层的方法，以及包括掩埋材料层的半导体装置。
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公开(公告)号：US07511353B2
公开(公告)日：2009-03-31
申请号：US10971572
申请日：2004-10-22
申请人： Anton Mauder , Frank Hille , Vytla Rajeev Krishna , Elmar Falck , Hans-Joachim Schulze , Franz-Josef Niedernostheide , Helmut Strack
发明人： Anton Mauder , Frank Hille , Vytla Rajeev Krishna , Elmar Falck , Hans-Joachim Schulze , Franz-Josef Niedernostheide , Helmut Strack
IPC分类号： H01L29/72
CPC分类号： H01L21/263 , H01L29/32 , H01L29/6609 , H01L29/861
摘要： A semiconductor diode (30) has an anode (32), a cathode (33) and a semiconductor volume (31) provided between the anode (32) and the cathode (33). An electron mobility and/or hole mobility within a zone (34) of the semiconductor volume (31) that is situated in front of the cathode (33) is reduced relative to the rest of the semiconductor volume (31).
摘要翻译： 半导体二极管（30）具有设置在阳极（32）和阴极（33）之间的阳极（32），阴极（33）和半导体体积（31）。 位于阴极（33）前方的半导体体积（31）的区域（34）内的电子迁移率和/或空穴迁移率相对于半导体体积（31）的其余部分减小。
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公开(公告)号：US06441408B2
公开(公告)日：2002-08-27
申请号：US09761241
申请日：2001-01-17
申请人： Alfred Porst , Helmut Strack , Anton Mauder , Hans-Joachim Schulze , Heinrich Brunner , Josef Bauer , Reiner Barthelmess
发明人： Alfred Porst , Helmut Strack , Anton Mauder , Hans-Joachim Schulze , Heinrich Brunner , Josef Bauer , Reiner Barthelmess
IPC分类号： H01L3300
CPC分类号： H01L29/1016 , H01L29/7395 , H01L29/7455 , H01L29/749
摘要： A power semiconductor components has stop zones. In order to optimize the static and dynamic losses of the power semiconductor components, the stop zone is provided with donors which have at least one donor level which lies within the band gap of silicon and is at least 200 meV away from the conduction band edge of silicon.
摘要翻译： 功率半导体元件具有停止区域。 为了优化功率半导体部件的静态和动态损耗，停止区域具有供体，其具有位于硅的带隙内的至少一个施主电平，并且距离导电带边缘至少200meV 硅。
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25.发明授权公开(公告)号：US08786012B2
公开(公告)日：2014-07-22
申请号：US13542737
申请日：2012-07-06
申请人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
发明人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
IPC分类号： H01L29/66
CPC分类号： H01L21/28194 , H01L21/02109 , H01L21/02145 , H01L21/0228 , H01L29/0653 , H01L29/0878 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/407 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/66734 , H01L29/7393 , H01L29/7394 , H01L29/7397 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L29/792 , H01L29/8611
摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.
摘要翻译： 功率半导体器件具有半导体本体，该半导体本体包括有源区域和限定半导体本体的水平主表面的周边区域。 半导体本体还包括n型半导体层，pn结和至少一个沟槽。 n型半导体层嵌入半导体本体中并延伸到周边区域的主表面。 pn结布置在有源区域中的n型半导体层和主表面之间。 至少一个沟槽在外围区域中从主表面延伸到n型半导体层中，并且包括具有固定的负电荷的电介质层。 在垂直方向上，介电层布置在pn结的下方和上方。 具有固定负电荷的电介质层通常具有负的净电荷。 此外，提供了一种用于形成半导体器件的方法。
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公开(公告)号：US08748974B2
公开(公告)日：2014-06-10
申请号：US13542737
申请日：2012-07-06
申请人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
发明人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
IPC分类号： H01L29/66
摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.
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27.发明申请公开(公告)号：US20120286355A1
公开(公告)日：2012-11-15
申请号：US13542737
申请日：2012-07-06
申请人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
发明人： Anton Mauder , Franz Hirler , Wolfgang Lehnert , Rudolf Berger , Klemens Pruegl , Hans-Joachim Schulze , Helmut Strack
IPC分类号： H01L29/78 , H01L21/302 , H01L29/02
CPC分类号： H01L21/28194 , H01L21/02109 , H01L21/02145 , H01L21/0228 , H01L29/0653 , H01L29/0878 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/407 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/66734 , H01L29/7393 , H01L29/7394 , H01L29/7397 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L29/792 , H01L29/8611
摘要： A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.
摘要翻译： 功率半导体器件具有半导体本体，该半导体本体包括有源区域和限定半导体本体的水平主表面的周边区域。 半导体本体还包括n型半导体层，pn结和至少一个沟槽。 n型半导体层嵌入半导体本体中并延伸到周边区域的主表面。 pn结布置在有源区域中的n型半导体层和主表面之间。 至少一个沟槽在外围区域中从主表面延伸到n型半导体层中，并且包括具有固定的负电荷的电介质层。 在垂直方向上，介电层布置在pn结的下方和上方。 具有固定负电荷的电介质层通常具有负的净电荷。 此外，提供了一种用于形成半导体器件的方法。
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公开(公告)号：US20090298270A1
公开(公告)日：2009-12-03
申请号：US12474464
申请日：2009-05-29
IPC分类号： H01L21/265
CPC分类号： H01L21/26513 , H01L21/263 , H01L21/26506 , H01L21/3242
摘要： A method for producing a semiconductor is disclosed. One embodiment provides a p-doped semiconductor body having a first side and a second side. An n-doped zone is formed in the semiconductor body by implantation of protons into the semiconductor body via the first side down to a specific depth of the semiconductor body and by subsequent heating at least of the proton-implanted region of the semiconductor body. A pn junction arises in the semiconductor body. The second side of the semiconductor body is removed at least as far as a space charge zone spanned at the pn junction.
摘要翻译： 公开了半导体的制造方法。 一个实施例提供了具有第一侧和第二侧的p掺杂半导体本体。 通过将半导体本体中的质子经由第一侧向下注入到半导体本体的特定深度并且随后至少加热半导体本体的质子注入区域，在半导体本体中形成n掺杂区。 在半导体体中产生pn结。 半导体主体的第二面至少与在pn结处跨过的空间电荷区域一样被去除。
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29.发明申请公开(公告)号：US20060244060A1
公开(公告)日：2006-11-02
申请号：US11455397
申请日：2006-06-19
IPC分类号： H01L29/76
CPC分类号： H01L29/7805 , H01L21/28512 , H01L21/28568 , H01L29/0634 , H01L29/0847 , H01L29/1095 , H01L29/167 , H01L29/32 , H01L29/456 , H01L29/7395 , H01L29/7802 , H01L29/7803 , H01L29/7813 , H01L29/861 , H01L29/8613
摘要： The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive metal-semiconductor contact is formed between the metallization and the semiconductor layer. The metallization and/or the semiconductor layer are formed in such a way that only a fraction of the introduced doping concentration is electrically active, and a semiconductor layer doped only with this fraction of the doping concentration only forms a Schottky contact when contact is made with the metallization. Furthermore, the invention relates to a semiconductor component comprising a drain zone, body zones embedded therein and source zones again embedded therein. The semiconductor component has metal-semiconductor contacts in which the contacts made contact only with the source zones but not with the body zones.
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30.发明授权Metal semiconductor contact, semiconductor component, integrated circuit arrangement and method 有权金属半导体接触，半导体元件，集成电路布置及方法公开(公告)号：US07087981B2
公开(公告)日：2006-08-08
申请号：US10419597
申请日：2003-04-21
IPC分类号： H01L29/207
CPC分类号： H01L29/7805 , H01L21/28512 , H01L21/28568 , H01L29/0634 , H01L29/0847 , H01L29/1095 , H01L29/167 , H01L29/32 , H01L29/456 , H01L29/7395 , H01L29/7802 , H01L29/7803 , H01L29/7813 , H01L29/861 , H01L29/8613
摘要： The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive metal-semiconductor contact is formed between the metallization and the semiconductor layer. The metallization and/or the semiconductor layer are formed in such a way that only a fraction of the introduced doping concentration is electrically active, and a semiconductor layer doped only with this fraction of the doping concentration only forms a Schottky contact when contact is made with the metallization. Furthermore, the invention relates to a semiconductor component comprising a drain zone, body zones embedded therein and source zones again embedded therein. The semiconductor component has metal-semiconductor contacts in which the contacts made contact only with the source zones but not with the body zones.
摘要翻译： 本发明涉及包含半导体层并包含施加到半导体层的金属化的金属 - 半导体接触，将高掺杂浓度引入到半导体层中，使得在金属化和金属化之间形成非反应性金属 - 半导体接触 半导体层。 金属化和/或半导体层以这样的方式形成，使得只有一部分引入的掺杂浓度是电活性的，并且仅当这一部分掺杂浓度掺杂的半导体层仅在与...接触时形成肖特基接触 金属化。 此外，本发明涉及一种半导体部件，其包括漏区，嵌入其中的主体区和再次嵌入其中的源区。 半导体部件具有金属半导体触点，触点仅与源极区域接触而不与主体区域接触。
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