公开(公告)号：US07723771B2

公开(公告)日：2010-05-25

申请号：US11731457

申请日：2007-03-30

申请人： Tim Boescke ,  Uwe Schroeder

发明人： Tim Boescke ,  Uwe Schroeder

IPC分类号： H01L27/108

CPC分类号： H01G4/1236 ,  H01G4/33 ,  H01L28/40 ,  Y10T29/417

摘要： A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed. The dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, whereas the dielectric structure deposited comprises a dopant content of 10 atomic percent or less of the deposited material excluding oxygen.

摘要翻译： 电容器结构包括导电材料的第一和第二电极。 在第一和第二电极之间，设置原子层沉积介电膜，其包括氧化锆和掺杂剂氧化物。 这里，掺杂剂包含从锆的离子半径相差大于24μm的离子半径，而电介质膜包含不含氧的电介质膜材料的10原子％以下的掺杂剂含量。 制造电容器的工艺包括形成电容器的底部电极的步骤。 在底部电极上沉​​积包含氧化锆的电介质膜，并且进行用于将掺杂剂氧化物引入电介质膜的步骤。 在电介质结构上，形成顶部电极。 掺杂剂包含距离锆的离子半径相差超过24μm的离子半径，而沉积的介电结构包括不含氧的沉积材料的10原子％以下的掺杂剂含量。

公开(公告)号：US20050106890A1

公开(公告)日：2005-05-19

申请号：US10937099

申请日：2004-09-08

申请人： Uwe Schroeder ,  Matthias Goldbach ,  Tobias Mono

发明人： Uwe Schroeder ,  Matthias Goldbach ,  Tobias Mono

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/302 ,  H01L21/308 ,  H01L21/461 ,  H01L21/8236 ,  H01L21/8246 ,  H01L21/8247

CPC分类号： H01L27/11568 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3086 ,  Y10S438/924

摘要： Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer (12). The resist ridge (20) serves as a mask for a subsequent implantation step (46). This makes use of an effect whereby the material of the hard mask layer (12), in a part (122) shaded by the resist ridge (20), can be etched out selectively with respect to the implanted part (121). The consequently patterned hard mask layer is used as an etching mask with respect to an underlying layer or layer stack (102-104) that is actually to be patterned. From the resist ridge (10) that has been formed as a line in the photosensitive resist (16), in a type of tone reversal, an opening (24) has been formed in the hard mask layer and a trench (26) has been formed in the layer/layer stack (102-104). According to the invention, the width (51, 52) of the resist ridge (20) is reduced by exposing the resist ridge (20) to an oxygen plasma (42). As a result, it is possible to form a trench (26) in the hard mask layer (12) and in the layer/layer stack (102-104) the width (52) of which trench is smaller than the lithographic resolution limit during the lithographic patterning of the resist (16).

摘要翻译： 优选使用正性抗蚀剂，在施加在硬掩模层（12）上方的半导体晶片（1）上的光敏抗蚀剂（16）中形成抗蚀剂脊（20）。 抗蚀剂脊（20）用作随后的注入步骤（46）的掩模。 这利用了可以相对于植入部分（121）选择性地蚀刻出由抗蚀剂脊（20）遮蔽的部分（122）中的硬掩模层（12）的材料的效果。 因此，图案化的硬掩模层相对于实际上被图案化的下层或多层叠层（102-104）用作蚀刻掩模。 从形成为光敏抗蚀剂（16）中的线的抗蚀剂脊（10）以一种音调反转形式，在硬掩模层中形成有开口（24），并且已经形成了沟槽（26） 形成在层/层堆叠（102-104）中。 根据本发明，通过将抗蚀剂脊（20）暴露于氧等离子体（42）来减小抗蚀剂脊（20）的宽度（51,52）。 结果，可以在硬掩模层（12）和层/层堆叠（102-104）中形成沟槽（26），其中沟槽的宽度（52）小于光刻分辨率极限 抗蚀剂（16）的平版印刷图案化。

公开(公告)号：US20070031737A1

公开(公告)日：2007-02-08

申请号：US11199012

申请日：2005-08-08

申请人： Uwe Schroeder ,  Klaus Herold

发明人： Uwe Schroeder ,  Klaus Herold

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/70433 ,  Y02T10/82

摘要： Lithography masks and methods of lithography for manufacturing semiconductor devices are disclosed. Forbidden pitches are circumvented by dividing a main feature into a set of two or more sub-features. The sum of the widths of the sub-features and the spaces between the sub-features is substantially equal to the width of the main feature. The set of two or more sub-features comprise a plurality of different distances between an adjacent set of two or more sub-features. At least one of the plurality of distances comprises a pitch that is resolvable by the lithography system, resulting in increased resolution for the main features, improved critical dimension (CD) control, and increased process windows.

摘要翻译： 公开了用于制造半导体器件的光刻掩模和光刻方法。 通过将主要特征分成一组两个或多个子特征来避免禁止的间距。 子特征的宽度和子特征之间的空间之和基本上等于主要特征的宽度。 两个或多个子特征的集合包括两个或多个子特征的相邻集合之间的多个不同距离。 多个距离中的至少一个包括由光刻系统可分辨的间距，导致主要特征提高的分辨率，改进的临界尺寸（CD）控制和增加的过程窗口。

公开(公告)号：US20060202250A1

公开(公告)日：2006-09-14

申请号：US11076021

申请日：2005-03-10

申请人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

发明人： Thomas Hecht ,  Uwe Schroeder ,  Till Schloesser ,  Stefan Jakschik ,  Alejandro Avellan

IPC分类号： H01L29/94

CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L28/82

摘要： A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.

摘要翻译： 适用于DRAM单元的存储电容器至少部分地形成在衬底表面之上，并且包括：至少部分地形成在衬底表面上方的存储电极，与存储电极相邻形成的电介质层和形成的对电极 所述对置电极通过所述电介质层与所述存储电极隔离，其中所述存储电极形成为主体，所述主体由平行于所述电介质层的平面中的具有在所述主体外部的曲率中心的至少一个曲面限定 基材表面。 根据另一种结构，存储电极形成为由具有两个相邻平面的至少一组限定的主体，两个平面相对于基板表面垂直延伸，两个平面的法线相交点位于外部 身体。

公开(公告)号：US06399490B1

公开(公告)日：2002-06-04

申请号：US09607131

申请日：2000-06-29

申请人： Rajarao Jammy ,  Cheryl G. Faltermeier ,  Uwe Schroeder ,  Kwong Hon Wong

发明人： Rajarao Jammy ,  Cheryl G. Faltermeier ,  Uwe Schroeder ,  Kwong Hon Wong

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  C23C16/045 ,  C23C16/34 ,  H01L21/28556 ,  H01L21/76852 ,  H01L21/7687 ,  H01L27/10861 ,  H01L28/82

摘要： Process for forming highly conformal titanium nitride on a silicon substrate. A gaseous reaction mixture of titanium tetrachloride and ammonia is passed over the semiconductor substrate surface maintained at a temperature of about 350° C. to about 800° C. The ratio of titanium tetrachloride to ammonia is about 5:1 to 20:1. The high degree of conformality achieved by the process of the invention allows TiN layers to be deposited on structures with high aspect ratios and on complicated, three-dimensional structures without forming a large seam or void.

摘要翻译： 在硅衬底上形成高保形氮化钛的工艺。 四氯化钛和氨的气态反应混合物通过保持在约350℃至约800℃的半导体衬底表面上。四氯化钛与氨的比例为约5：1至20：1。 通过本发明的方法实现的高度的保形性允许TiN层沉积在具有高纵横比的结构上和复杂的三维结构上，而不形成大的接缝或空隙。

公开(公告)号：US20070134909A1

公开(公告)日：2007-06-14

申请号：US11301515

申请日：2005-12-13

申请人： Veit Klee ,  Roman Knoefler ,  Uwe Schroeder

发明人： Veit Klee ,  Roman Knoefler ,  Uwe Schroeder

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

摘要： To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

摘要翻译： 为了形成半导体器件，在导电区域上形成绝缘层，并且在绝缘层上形成图案转移层。 图案转印层以要形成在绝缘层中的凹槽布局的相反色调被图案化，使得图案转印层保留在要形成凹部的区域上。 掩模材料形成在绝缘层上并与图案转印层对准。 去除图案转印层的剩余部分，并使用掩模材料作为掩模在绝缘层中蚀刻凹陷。

公开(公告)号：US20070102397A1

公开(公告)日：2007-05-10

申请号：US11270400

申请日：2005-11-09

申请人： Uwe Schroeder

发明人： Uwe Schroeder

IPC分类号： C23F1/00 ,  H01L21/311 ,  B44C1/22

CPC分类号： H01L21/76816 ,  Y10S430/151

摘要： A method for printing contacts utilizes photolithographic pattern reversal. A negative of the contact is printed on a resist layer. Unexposed portions of the resist layer are stripped to expose a first layer. The first layer is etched to remove exposed portions of the first layer not covered by the negative of the contact and to expose a second layer. A pattern reversal is performed to cure exposed portions of the second layer not covered by the first layer.

摘要翻译： 用于印刷触点的方法利用光刻图案反转。 接触的负片印刷在抗蚀剂层上。 去除抗蚀剂层的未曝光部分以露出第一层。 蚀刻第一层以除去未被接触物的负极覆盖的第一层的暴露部分并暴露第二层。 执行图案反转以固化未被第一层覆盖的第二层的暴露部分。

公开(公告)号：US20050106475A1

公开(公告)日：2005-05-19

申请号：US10952559

申请日：2004-09-28

申请人： Uwe Schroeder ,  Oliver Broermann

发明人： Uwe Schroeder ,  Oliver Broermann

IPC分类号： A47G1/12 ,  B44F1/00 ,  G03C5/00 ,  G03F1/48 ,  G03F1/62 ,  G03F9/00 ,  G21K5/00 ,  H01L21/8238

CPC分类号： G03F1/62 ,  G03F1/48

摘要： A lithographic mask having a mask substrate (3) and a patterned mask layer (4) which includes mask structures (5) and can be transferred by lithography to a further substrate is disclosed. With masks of this type, it is customary for a protective layer to be provided in the form of a membrane positioned at a distance from the mask layer (4), in order to keep impurity particles or other impurities away from the focal plane of the mask layer (4). According to the invention, the protective layer (6) is applied in liquid form directly to the mask structures (5) and fills up spaces between the mask structures (4). Then, the protective layer (6), while it is still in the liquid state, is covered with a plane-parallel plate. The continuously dense protective layer (6) which is formed in accordance with the invention is even more reliable in preventing impurity particles or impurities (20) from penetrating into spacers between the structures (5) of the mask layer (4). The impurity particles or impurities (20) can only be deposited on the outer side (16) of the protective layer (6), at a still greater distance from the focal plane.

摘要翻译： 公开了一种具有掩模衬底（3）和包括掩模结构（5）的图案化掩模层（4）并且可以通过光刻转移到另一衬底的光刻掩模。 对于这种类型的掩模，通常保护层以与掩模层（4）相距一定距离的膜的形式提供，以便使杂质颗粒或其它杂质远离所述掩模层（4）的焦平面 掩模层（4）。 根据本发明，保护层（6）以液体形式直接施加到掩模结构（5）并填充掩模结构（4）之间的空间。 然后，保护层（6）仍处于液体状态时被平面平行板覆盖。 根据本发明形成的连续致密保护层（6）在防止杂质颗粒或杂质（20）渗透到掩模层（4）的结构（5）之间的间隔物中是更可靠的。 杂质颗粒或杂质（20）只能在与焦平面更远的距离处沉积在保护层（6）的外侧（16）上。

公开(公告)号：US06403423B1

公开(公告)日：2002-06-11

申请号：US09713272

申请日：2000-11-15

申请人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made-smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些电介质间隔物允许阵列栅极导体抗蚀剂线被制成 - 小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：US07939137B2

公开(公告)日：2011-05-10

申请号：US10478143

申请日：2002-05-16

申请人： Klaus Becker-Weimann ,  Oliver Büker ,  Uwe Schroeder

发明人： Klaus Becker-Weimann ,  Oliver Büker ,  Uwe Schroeder

IPC分类号： B05D3/02

CPC分类号： B05D5/00 ,  B05D1/265 ,  B05D1/28 ,  B05D7/08 ,  B05D2503/00

摘要： The invention relates to a method and a device for producing parts (1) having a sealing layer (2) on the surface, and corresponding parts. Said method and device are improved in that the sealing layer (2) is applied to the surface in the form of a water-free and solvent-free reactive hot melt layer based on polyurethane and hardened by atmospheric humidity, and the inventive device comprises an application station (6), a transport device (5) and a smoothing station (8).

摘要翻译： 本发明涉及一种用于制造在表面上具有密封层（2）的部件（1）和相应部件的方法和装置。 所述方法和装置的改进在于，密封层（2）以基于聚氨酯的无水和无溶剂的反应性热熔体层的形式施加到表面，并且由大气湿度硬化，并且本发明的装置包括 应用站（6），传送设备（5）和平滑站（8）。