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    Method for forming a trench in a layer or a layer stack on a semiconductor wafer
    1.
    发明申请
    Method for forming a trench in a layer or a layer stack on a semiconductor wafer 有权
    在半导体晶片上的层或层叠中形成沟槽的方法

    公开(公告)号：US20050106890A1

    公开(公告)日：2005-05-19

    申请号：US10937099

    申请日：2004-09-08

    申请人： Uwe Schroeder ,  Matthias Goldbach ,  Tobias Mono

    发明人： Uwe Schroeder ,  Matthias Goldbach ,  Tobias Mono

    IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/302 ,  H01L21/308 ,  H01L21/461 ,  H01L21/8236 ,  H01L21/8246 ,  H01L21/8247

    CPC分类号： H01L27/11568 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3086 ,  Y10S438/924

    摘要： Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer (12). The resist ridge (20) serves as a mask for a subsequent implantation step (46). This makes use of an effect whereby the material of the hard mask layer (12), in a part (122) shaded by the resist ridge (20), can be etched out selectively with respect to the implanted part (121). The consequently patterned hard mask layer is used as an etching mask with respect to an underlying layer or layer stack (102-104) that is actually to be patterned. From the resist ridge (10) that has been formed as a line in the photosensitive resist (16), in a type of tone reversal, an opening (24) has been formed in the hard mask layer and a trench (26) has been formed in the layer/layer stack (102-104). According to the invention, the width (51, 52) of the resist ridge (20) is reduced by exposing the resist ridge (20) to an oxygen plasma (42). As a result, it is possible to form a trench (26) in the hard mask layer (12) and in the layer/layer stack (102-104) the width (52) of which trench is smaller than the lithographic resolution limit during the lithographic patterning of the resist (16).

    摘要翻译： 优选使用正性抗蚀剂，在施加在硬掩模层（12）上方的半导体晶片（1）上的光敏抗蚀剂（16）中形成抗蚀剂脊（20）。 抗蚀剂脊（20）用作随后的注入步骤（46）的掩模。 这利用了可以相对于植入部分（121）选择性地蚀刻出由抗蚀剂脊（20）遮蔽的部分（122）中的硬掩模层（12）的材料的效果。 因此，图案化的硬掩模层相对于实际上被图案化的下层或多层叠层（102-104）用作蚀刻掩模。 从形成为光敏抗蚀剂（16）中的线的抗蚀剂脊（10）以一种音调反转形式，在硬掩模层中形成有开口（24），并且已经形成了沟槽（26） 形成在层/层堆叠（102-104）中。 根据本发明，通过将抗蚀剂脊（20）暴露于氧等离子体（42）来减小抗蚀剂脊（20）的宽度（51,52）。 结果，可以在硬掩模层（12）和层/层堆叠（102-104）中形成沟槽（26），其中沟槽的宽度（52）小于光刻分辨率极限 抗蚀剂（16）的平版印刷图案化。

    Method for fabricating an electrical component
    5.
    发明授权
    Method for fabricating an electrical component 有权
    电气部件的制造方法

    公开(公告)号：US07531406B2

    公开(公告)日：2009-05-12

    申请号：US11399811

    申请日：2006-04-07

    申请人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

    发明人： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

    IPC分类号： H01L21/8234

    CPC分类号： H01L28/65 ,  H01L27/1087 ,  H01L29/66181

    摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.

    摘要翻译： 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。

    Effective assist pattern for nested and isolated contacts
    6.
    发明申请
    Effective assist pattern for nested and isolated contacts 有权
    嵌套和隔离接触的有效辅助模式

    公开(公告)号：US20050136336A1

    公开(公告)日：2005-06-23

    申请号：US10739423

    申请日：2003-12-18

    申请人： Jochen Schacht ,  Uwe Schroeder ,  Benjamin Lin

    发明人： Jochen Schacht ,  Uwe Schroeder ,  Benjamin Lin

    IPC分类号： G03F1/14 ,  G03F9/00

    CPC分类号： G03F1/36

    摘要： A photomask with desired illumination conditions can be constructed by combining a base pattern of openings with an assist pattern which includes openings that are offset from respectively corresponding openings of the base pattern by a preset angular distance.

    摘要翻译： 具有期望的照明条件的光掩模可以通过将开口的基本图案与辅助图案组合而构成，该辅助图案包括从底座图案的相应开口偏移预定角距离的开口。

    Semiconductor structures and manufacturing methods
    7.
    发明授权
    Semiconductor structures and manufacturing methods 有权
    半导体结构及制造方法

    公开(公告)号：US06605860B1

    公开(公告)日：2003-08-12

    申请号：US09597442

    申请日：2000-06-20

    申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

    发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

    IPC分类号： H01L2906

    CPC分类号： H01L21/28202 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/2822 ,  H01L21/3144 ,  H01L21/31658 ,  H01L27/10864 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S257/905

    摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

    摘要翻译： 一种在硅主体上形成基本上均匀的厚的热生长二氧化硅材料的方法，其独立于凸轮轴。 沟槽形成在硅体的表面中，这样的沟槽具有设置在不同结晶平面中的侧壁，这些平面中的一个是100晶体平面，另外一个这样的平面是“10”平面。 在侧壁上形成基本均匀的氮化硅层。 具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅 具有比<110>平面上的厚度大于超过<100>平面的厚度。 对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分 在氮化硅材料的下面部分上的<110>面上的二氧化硅。 选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。 然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

    Zirconium oxide based capacitor and process to manufacture the same
    9.
    发明授权
    Zirconium oxide based capacitor and process to manufacture the same 有权
    基于氧化锆的电容器及其制造方法

    公开(公告)号：US07723771B2

    公开(公告)日：2010-05-25

    申请号：US11731457

    申请日：2007-03-30

    申请人： Tim Boescke ,  Uwe Schroeder

    发明人： Tim Boescke ,  Uwe Schroeder

    IPC分类号： H01L27/108

    CPC分类号： H01G4/1236 ,  H01G4/33 ,  H01L28/40 ,  Y10T29/417

    摘要： A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed. The dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, whereas the dielectric structure deposited comprises a dopant content of 10 atomic percent or less of the deposited material excluding oxygen.

    摘要翻译： 电容器结构包括导电材料的第一和第二电极。 在第一和第二电极之间，设置原子层沉积介电膜，其包括氧化锆和掺杂剂氧化物。 这里，掺杂剂包含从锆的离子半径相差大于24μm的离子半径，而电介质膜包含不含氧的电介质膜材料的10原子％以下的掺杂剂含量。 制造电容器的工艺包括形成电容器的底部电极的步骤。 在底部电极上沉​​积包含氧化锆的电介质膜，并且进行用于将掺杂剂氧化物引入电介质膜的步骤。 在电介质结构上，形成顶部电极。 掺杂剂包含距离锆的离子半径相差超过24μm的离子半径，而沉积的介电结构包括不含氧的沉积材料的10原子％以下的掺杂剂含量。