公开(公告)号：US5156991A

公开(公告)日：1992-10-20

申请号：US648087

申请日：1991-01-31

申请人： Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

发明人： Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L29/7883 ,  Y10S438/981

摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between wordlines is also by thick thermal oxide in a preferred embodiment, further improving the coupling ratio. Bitline and wordline spacing may be selected for optimum pitch or aspect ratio. Bitline to substrate capacitance is minimized.

摘要翻译： 使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了 易于制造和减小电池尺寸。 位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 隧道窗口提供的编程和擦除靠近或高于源的通道侧。 窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。 通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。 在优选实施例中，字线之间的隔离也是厚氧化物，进一步提高了耦合比。 可以选择位线和字线间距来获得最佳间距或宽高比。 位线到基板电容最小化。

公开(公告)号：US20090034338A1

公开(公告)日：2009-02-05

申请号：US12102125

申请日：2008-04-14

申请人： Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

发明人： Sung-Wei Lin ,  Stephen Keith Heinrich-Barna

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/28 ,  G11C16/30

摘要： One embodiment of the invention includes a memory system. The system comprises a memory cell coupled to a bit-line node. The memory cell can be configured to generate a bit-line current on the bit-line node in response to a bias voltage during a read operation. The system further comprises a sense amplifier configured to maintain a substantially constant voltage magnitude of the bit-line node during a pre-charge phase and a sense phase of the read operation based on regulating current flow to and from the bit-line node, and to determine a memory value of the flash memory transistor during the read operation based on a magnitude of the bit-line current on the bit-line node.

摘要翻译： 本发明的一个实施例包括存储器系统。 该系统包括耦合到位线节点的存储器单元。 存储器单元可被配置为在读取操作期间响应于偏置电压而在位线节点上产生位线电流。 该系统还包括读出放大器，其被配置为在预充电阶段期间保持位线节点的基本上恒定的电压幅值，并且基于调节到位线节点和从位线节点的电流流动来读取操作的感测相位，以及 以在读取操作期间基于位线节点上的位线电流的大小来确定闪存晶体管的存储器值。

公开(公告)号：US07349237B2

公开(公告)日：2008-03-25

申请号：US11003707

申请日：2004-12-03

申请人： Sung-Wei Lin ,  Sudhir K. Madan ,  John Fong

发明人： Sung-Wei Lin ,  Sudhir K. Madan ,  John Fong

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： H03K19/00346 ,  H03K19/185

摘要： A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

摘要翻译： 公开了一种减少字线耦合的存储电路和方法。 电路包括排列成行（702,704和706）和列（750,752）的多个存储单元。 第一导体（710,850）耦合到存储器单元的多个行（702,704和706）。 第一晶体管（810）具有耦合在电压源端子（800）和第一导体（850）之间的电流通路和耦合以接收第一控制信号（PLV）的控制端子。 第二晶体管（820）具有耦合在电压供应端和第一导体之间的电流路径，以及耦合以接收第二控制信号（PLW）的控制端。

公开(公告)号：US06826103B2

公开(公告)日：2004-11-30

申请号：US10284061

申请日：2002-10-30

申请人： Nathan I. Moon ,  Richard K. Eguchi ,  Sung-Wei Lin

发明人： Nathan I. Moon ,  Richard K. Eguchi ,  Sung-Wei Lin

IPC分类号： G11C702

CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C7/14 ,  G11C16/04 ,  G11C16/12 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5006 ,  G11C2207/2254

摘要： Methods and apparatus for trimming a reference circuit. A representative technique includes transmitting a constant signal (e.g., a constant current or voltage). The constant signal is received (e.g., at a device pin or other contact). The constant signal is compared to a reference signal. Variables are obtained for program/erase pulses from a user. The reference circuit signal is adjusted to match the constant signal by sending program/erase pulses to the reference circuit. The program/erase pulses are set based on the variables for program/erase pulses and a result of comparing the constant signal with the reference signal.

摘要翻译： 用于修整参考电路的方法和装置。 代表性技术包括传输恒定信号（例如恒定电流或电压）。 接收恒定信号（例如，在设备引脚或其他接点处）。 将恒定信号与参考信号进行比较。 获得用户编程/擦除脉冲的变量。 通过向参考电路发送编程/擦除脉冲来调整参考电路信号以匹配恒定信号。 基于编程/擦除脉冲的变量设置编程/擦除脉冲，以及将恒定信号与参考信号进行比较的结果。

公开(公告)号：US5523249A

公开(公告)日：1996-06-04

申请号：US364529

申请日：1994-12-23

申请人： Manzur Gill ,  David J. McElroy ,  Sung-Wei Lin ,  Inn K. Lee

发明人： Manzur Gill ,  David J. McElroy ,  Sung-Wei Lin ,  Inn K. Lee

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17 ). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.

摘要翻译： 在半导体衬底（22）的表面上成对地形成电可擦除的电可编程的只读存储单元阵列。 每个存储单元包括源极区域（11）和漏极区域（12），其间具有相应的沟道区域。 福勒 - 诺德海姆隧道窗口（13a）位于连接到源（11）的源极线（17）上。 浮动门（13）包括隧道窗部分。 控制栅极（14）设置在浮置栅极（13）上，由中间层间电介质（27）绝缘。 浮动栅极（13）和控制栅极（14）包括通道部分（Ch）。 通道部分（Ch）用作源（11）和漏极（12）区域的自对准注入掩模，使得沟道结边缘与通道部分（Ch）的相应边缘对齐。 存储单元通过从通道的热载流子注入到浮动栅极（13）进行编程，并由Fowler-Nordheim从浮动栅极（13）通过隧道窗口（13a）到源极线（17）的隧道擦除， 。 单元的程序和擦除区域在物理上彼此分离，并且这些区域中的每一个的特性，包括氧化物可以彼此独立地最优化。

公开(公告)号：US5335200A

公开(公告)日：1994-08-02

申请号：US756

申请日：1993-01-05

申请人： Tim M. Coffman ,  Sung-Wei Lin

发明人： Tim M. Coffman ,  Sung-Wei Lin

IPC分类号： G11C5/14 ,  G11C16/14 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/14 ,  G11C16/30 ,  G11C5/145

摘要： An improved negative charge pump system for erasing a memory array in a memory which has a supply voltage and a negative charge pump. The negative charge pump system includes (a) a device for selecting a memory array to be erased; (b) a device for switching on the supply voltage Vnn for the charge pump; (c) a device for pumping the supply voltage Vnn with the charge pump to produce a pumped negative voltage; (d) a device for erasing the selected array with the pumped negative voltage; (e) a device for stopping the pumping; and (f) a device for providing a discharge path for voltages trapped in the charge pump.

摘要翻译： 一种改进的负电荷泵系统，用于擦除具有电源电压和负电荷泵的存储器中的存储器阵列。 负电荷泵系统包括（a）用于选择要擦除的存储器阵列的装置; （b）用于接通电荷泵的电源电压Vnn的装置; （c）用电荷泵泵浦电源电压Vnn以产生泵送的负电压的装置; （d）用抽吸负电压擦除所选阵列的装置; （e）停止泵送的装置; 以及（f）用于为电荷泵中捕获的电压提供放电路径的装置。

公开(公告)号：US5017980A

公开(公告)日：1991-05-21

申请号：US494051

申请日：1990-03-15

申请人： Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

发明人： Manzur Gill ,  Sebastiano D'Arrigo ,  Sung-Wei Lin

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L29/7883

摘要： An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between cells in the wordline direction is by a self-aligned implanted region, in this embodiment.

摘要翻译： 使用与浮栅晶体管合并的增强晶体管构造电可擦除可编程ROM单元或EEPROM单元，其中浮栅晶体管具有小的隧道窗，无接触电池布局，增强了 易于制造和减小电池尺寸。 位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由位于源的通道侧附近或上方的隧道窗口区域提供。 窗口具有比浮动栅极的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。 通过使用专用的漏极或接地线，而不是虚拟接地布局，并且通过使用厚氧化物在位线之间隔离，浮动栅极可以延伸到相邻的位线和隔离区域，从而产生良好的耦合比。 在本实施例中，字线方向上的单元之间的隔离是通过自对准注入区域。

公开(公告)号：US20070211510A1

公开(公告)日：2007-09-13

申请号：US11409628

申请日：2006-04-24

申请人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

发明人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

IPC分类号： G11C11/22 ,  G11C5/06 ,  G11C11/42

CPC分类号： G11C11/22 ,  H01L27/11502

摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

摘要翻译： 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

公开(公告)号：US5694073A

公开(公告)日：1997-12-02

申请号：US560768

申请日：1995-11-21

申请人： Timothy J. Coots ,  Phat C. Truong ,  Sung-Wei Lin ,  Tim M. Coffman ,  Ming-Bo Liu ,  Ronald J. Syzdek

发明人： Timothy J. Coots ,  Phat C. Truong ,  Sung-Wei Lin ,  Tim M. Coffman ,  Ming-Bo Liu ,  Ronald J. Syzdek

IPC分类号： G01K7/00 ,  G01R19/00 ,  G05F3/24 ,  G05F3/26 ,  H03K17/14 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  G05F3/02

CPC分类号： G05F3/262 ,  G05F3/247 ,  H03K19/00384

摘要： A supply-voltage detecting stage (11) that supplies first and second reference currents (I.sub.REFP and I.sub.REFN) which vary with the supply voltage (V.sub.cc) and are coupled by first and second gain stages (12A and 12B), respectively, to first and second temperature-detecting stages (13A and 13B), respectively. First and second temperature-detecting stages (13A and 13B) increase the coupled reference currents (I.sub.REFP and I.sub.REFN), respectively, to compensate for temperature increase through use temperature-sensitive, long-channel transistors (M34-M37 and M42-M45), supplying temperature and supply-voltage compensated output bias voltages at output terminals (MIRN and MIRP).

摘要翻译： 电源电压检测级（11），其提供第一和第二参考电流（IREFP和IREFN），其随着电源电压（Vcc）而变化并分别由第一和第二增益级（12A和12B）耦合到第一和第二增益级 第二温度检测级（13A和13B）。 第一和第二温度检测级（13A和13B）分别增加耦合的参考电流（IREFP和IREFN），以通过使用温度敏感的长沟道晶体管（M34-M37和M42-M45）补偿温度升高， 在输出端子（MIRN和MIRP）提供温度和电源电压补偿输出偏置电压。

公开(公告)号：US5491809A

公开(公告)日：1996-02-13

申请号：US764

申请日：1993-01-05

申请人： Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy

发明人： Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/22 ,  G11C16/34 ,  G06F12/16

CPC分类号： G11C16/3445 ,  G11C16/22 ,  G11C16/344

摘要： A method for erasing blocks of a non-volatile memory includes detecting whether a block is in at least one of an erased state or a state secured from erasure; then setting a flag register at a first level for each block detected to be in at least one of an erased state or a state secured from erasure or at a second level for each block not so detected; then selecting for erasure blocks that have their respective flags set at the second level; and then erasing the selected blocks.

摘要翻译： 一种用于擦除非易失性存储器的块的方法，包括：检测块是否处于擦除状态或从擦除中保护的状态中的至少一个; 然后将每个被检测到的块中的每个块设置为处于擦除状态或从擦除保护的状态中的至少一个或者对于不被检测到的每个块的第二级的标志寄存器; 然后选择其各自的标志设置在第二级的擦除块; 然后擦除所选的块。