公开(公告)号：US06368958B2

公开(公告)日：2002-04-09

申请号：US09876598

申请日：2001-06-08

申请人： Paul Kwok Keung Ho ,  Subhash Gupta ,  Mei Sheng Zhou ,  Simon Chooi

发明人： Paul Kwok Keung Ho ,  Subhash Gupta ,  Mei Sheng Zhou ,  Simon Chooi

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C18/1608 ,  C25D7/123 ,  H01L21/288 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877

摘要： A new method of depositing a copper layer, using disproportionation of Cu(I) ions from a solution stabilized by a polar organic solvent, for single and dual damascene interconnects in the manufacture of an integrated circuit device has been achieved. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer is patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer is deposited overlying the dielectric layer to line the vias and trenches. A simple Cu(I) ion solution, stabilized by a polar organic solvent, is coated overlying said barrier layer. Water is added to the stabilized simple Cu(I) ion solution to cause disproportionation of the simple Cu(I) ion from the Cu(I) ion solution. A copper layer is deposited overlying the barrier layer. The copper layer may comprise a thin seed layer for use in subsequent electroplating or electroless plating of copper or may comprise a thick copper layer to fill the vias and trenches. The integrated circuit is completed.

摘要翻译： 已经实现了在制造集成电路器件中使用Cu（I）离子从由极性有机溶剂稳定的溶液中进行歧化的单层和双镶嵌互连的沉积铜层的新方法。 提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。 图案化电介质层以形成用于计划的双镶嵌互连的通孔和沟槽。 沉积覆盖在介电层上的阻挡层以对通孔和沟槽进行排列。 将由极性有机溶剂稳定的简单的Cu（I）离子溶液涂覆在所述阻挡层上。 向稳定化的简单的Cu（I）离子溶液中加入水以引起Cu（I）离子溶液中简单的Cu（I）离子的歧化。 沉积在屏障层上的铜层。 铜层可以包括用于铜的后续电镀或无电镀的薄种子层，或者可以包括用于填充通孔和沟槽的厚铜层。 集成电路完成。

公开(公告)号：US07060613B2

公开(公告)日：2006-06-13

申请号：US10988692

申请日：2004-11-15

申请人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi

发明人： Simon Chooi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

公开(公告)号：US06365508B1

公开(公告)日：2002-04-02

申请号：US09618264

申请日：2000-07-18

申请人： Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi ,  Simon Chooi ,  Yakub Aliyu

发明人： Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi ,  Simon Chooi ,  Yakub Aliyu

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76826

摘要： A new method to avoid post-etch cleaning in a metallization process is described. An insulating layer is formed over a first metal line in a dielectric layer overlying a semiconductor substrate. A via opening is etched through the insulating layer to the first metal line whereby a polymer forms on sidewalls of the via opening. The polymer is treated with a fluorinating agent whereby the polymer is converted to an inert layer. Thereafter, a second metal line is formed within the via opening wherein the inert layer acts is as a barrier layer to complete the metallization process in the fabrication of an integrated circuit device.

摘要翻译： 描述了在金属化过程中避免蚀刻后清洁的新方法。 在覆盖半导体衬底的电介质层中的第一金属线上形成绝缘层。 通孔开口通过绝缘层蚀刻到第一金属线，由此在通孔开口的侧壁上形成聚合物。 用氟化剂处理聚合物，由此将聚合物转化为惰性层。 此后，在通孔开口内形成第二金属线，其中惰性层作为阻挡层，以在集成电路器件的制造中完成金属化工艺。

公开(公告)号：US06348407B1

公开(公告)日：2002-02-19

申请号：US09805955

申请日：2001-03-15

申请人： Subhash Gupta ,  Yi Xu ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Yi Xu ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： H01L214763

CPC分类号： H01L21/76826 ,  H01L21/31058 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76829

摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material is a silicon containing material and is transformed into a low dielectric constant material (k=3.5 to 5), which becomes silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.

摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及在双镶嵌互连中使用改进低介电常数有机材料之间的粘附性的交替蚀刻停止。 此外，蚀刻停止材料是含硅材料，并被转变成低介电常数材料（k = 3.5至5），其在UV辐射和甲硅烷基化之后变成富氧氧化硅，氧等离子体。

公开(公告)号：US06274499B1

公开(公告)日：2001-08-14

申请号：US09442493

申请日：1999-11-19

申请人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

发明人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

IPC分类号： H01L21302

CPC分类号： H01L21/76801 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76807 ,  H01L21/76834

摘要： In accordance with the objects of this invention a new method to prevent copper contamination of the intermetal dielectric layer during etching, CMP, or post-etching and post-CMP cleaning by forming a dielectric cap for isolation of the underlying dielectric layer is described. In one embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A via is patterned and filled with a metal layer and planarized. A copper layer is deposited overlying the planarized metal layer and dielectric cap layer. The copper layer is etched to form a copper line wherein the dielectric cap layer prevents copper contamination of the dielectric layer during etching and cleaning. In another embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A dual damascene opening is formed through the dielectric cap layer and the dielectric layer. A copper layer is deposited overlying a barrier metal layer over the dielectric cap layer and filling the dual damascene opening. The copper layer is polished back to leave the copper layer only within the dual damascene opening where the dielectric cap layer prevents copper contamination of the dielectric layer during polishing and cleaning.

摘要翻译： 根据本发明的目的，描述了通过形成用于隔离下面介电层的电介质盖，在蚀刻，CMP或后蚀刻和后CMP清洗中防止金属间电介质层的铜污染的新方法。 在本发明的一个实施例中，提供覆盖在半导体衬底上的电介质层。 介电覆盖层沉积在介电层上。 通孔被图案化并填充有金属层并且被平坦化。 沉积在平坦化的金属层和电介质盖层上的铜层。 铜层被蚀刻以形成铜线，其中电介质盖层在蚀刻和清洁期间防止电介质层的铜污染。 在本发明的另一个实施例中，提供覆盖半导体衬底的电介质层。 介电覆盖层沉积在介电层上。 通过电介质盖层和电介质层形成双镶嵌开口。 将铜层沉积在电介质盖层上方的阻挡金属层上，并填充双镶嵌开口。 将铜层抛光回来，仅在双镶嵌开口中留下铜层，其中介电盖层在抛光和清洁期间防止电介质层的铜污染。

公开(公告)号：US06251786B1

公开(公告)日：2001-06-26

申请号：US09390783

申请日：1999-09-07

申请人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

发明人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

IPC分类号： H01L2100

CPC分类号： H01L21/76834 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.

摘要翻译： 在电介质层中产生双镶嵌结构，该结构包含阻挡层，而覆盖层可以设置在电介质层上，也可以不设置在电介质层上，以进一步保护双镶嵌结构。 双镶嵌结构中的铜的表面是凹进的，通过CMP或等离子体蚀刻沉积并平面化/部分去除薄膜，从而在双镶嵌结构的铜上方提供坚固的表面，防止该镶嵌结构的凹陷和侵蚀 表面。

公开(公告)号：US06184138B2

公开(公告)日：2001-02-06

申请号：US09390782

申请日：1999-09-07

申请人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

发明人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： A new method is provided to construct a copper dual damascene structure. A layer of IMD is deposited over the surface of a substrate. A cap layer is deposited over this layer of IMD, the dual damascene structure is then patterned through the cap layer and into the layer of IMD. A barrier layer is blanket deposited, a copper seed layer is deposited over the barrier layer. The dual damascene structure is then filled with a spin-on material. The barrier layer and the copper seed layer are removed above the cap layer; the cap layer can be partially removed or can be left in place. The spin on material remains in place in the via and trench opening during the operation of removing the copper seed layer and the barrier layer from above the cap surface thereby protecting the inside surfaces of these openings. The spin-on material is next removed from the dual damascene structure and copper is deposited. The cap layer that is still present above the surface of the IMD protects the dielectric from being contaminated with copper solution during the deposition of the copper. The excess copper is removed using a touch-up CMP. The cap layer over the surface of the IMD can, after the copper has been deposited, be removed if this is so desired. As a final step in the process, a liner or oxidation/diffusion protection layer is deposited over the dual damascene structure and its surrounding area.

摘要翻译： 提供了一种构建铜双镶嵌结构的新方法。 一层IMD沉积在衬底的表面上。 覆盖层沉积在IMD的该层上，然后将双镶嵌结构通过盖层图案化并进入IMD层。 阻挡层被覆盖沉积，铜晶种层沉积在阻挡层上。 然后用镶嵌材料填充双镶嵌结构。 在盖层上除去阻挡层和铜籽晶层; 盖层可以被部分地去除或可以留在原处。 在从盖表面上方去除铜种子层和阻挡层的操作期间，材料上的旋转保持在通孔和沟槽开口中的适当位置，从而保护这些开口的内表面。 随后从双镶嵌结构中去除旋涂材料，并沉积铜。 仍然存在于IMD表面之上的盖层保护铜在沉积期间不被铜溶液污染。 使用上层CMP去除多余的铜。 如果这样做是希望的话，在沉积铜之后，IMD表面上的盖层可以被去除。 作为该方法的最后一步，衬垫或氧化/扩散保护层沉积在双镶嵌结构及其周围区域上。

公开(公告)号：US06225221B1

公开(公告)日：2001-05-01

申请号：US09501966

申请日：2000-02-10

申请人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta ,  Chockalingam Ramasamy

发明人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta ,  Chockalingam Ramasamy

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76874 ,  H01L21/76876 ,  H01L2221/1089

摘要： A new method of depositing a copper seed layer in the manufacture of an integrated circuit device has been achieved. The copper seed layer is thin and conformal and well-suited for subsequent electroless plating of copper. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer comprising tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer, and the integrated circuit is completed.

摘要翻译： 已经实现了在制造集成电路器件中沉积铜种子层的新方法。 铜种子层薄且保形，非常适合随后的铜化学镀。 提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。 图案化的电介质层形成用于计划的双镶嵌互连的通孔和沟槽。 包含钽，钛或钨的阻挡层沉积在电介质层上，以对通孔和沟槽进行排列。 通过CuF2蒸汽与阻挡层的反应沉积覆盖阻挡层的铜籽晶层，并且集成电路完成。

公开(公告)号：US06565664B2

公开(公告)日：2003-05-20

申请号：US10131519

申请日：2002-04-24

申请人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Simon Chooi ,  Paul Ho ,  Mei Sheng Zhou

IPC分类号： C23G114

CPC分类号： H01L21/32134 ,  C23F1/34 ,  H01L21/7684 ,  Y10S134/902

摘要： An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

公开(公告)号：US06465888B2

公开(公告)日：2002-10-15

申请号：US10043604

申请日：2002-01-14

申请人： Simon Chooi ,  Subhash Gupta ,  Mei Sheng Zhou ,  Sang Ki Hong

发明人： Simon Chooi ,  Subhash Gupta ,  Mei Sheng Zhou ,  Sang Ki Hong

IPC分类号： H01L2352

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76855

摘要： A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure—single, dual, or multi-structure—is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer. In the third embodiment, the ternary metal silicon nitride spacer is formed by etching after having first formed the amorphous silicon layer and the nitride layer, in that order, and then etching the passivation/barrier layer at the bottom of the damascene structure into the underlying copper layer. In all three embodiments, metal nitride reacts with amorphous silicon to form a ternary metal silicon nitride having an excellent property of adhering to copper while at the same time for forming an excellent barrier to diffusion of copper.

摘要翻译： 公开了一种形成非晶硅间隔物的方法，随后在铜镶嵌结构 - 单，双或多结构中在间隔物上形成金属氮化物，以防止铜中氟化物的形成。 在第一实施例中，通过在形成在内部的非晶硅间隔物上形成金属氮化物层之后，通过从双镶嵌结构形成开口到下面的铜层来形成铜镶嵌层和下面的铜金属层之间的互连 双镶嵌结构的墙壁。 在第二实施例中，通过在形成非晶硅间隔物之后并且在形成金属氮化物层之前通过蚀刻到下面的铜层中，由双镶嵌结构制造双镶嵌结构和下面的铜线之间的互连。 在第三实施例中，三元金属氮化硅间隔物依次先形成非晶硅层和氮化物层后，通过蚀刻形成，然后在镶嵌结构底部蚀刻钝化/阻挡层，形成底层 铜层。 在所有三个实施例中，金属氮化物与非晶硅反应形成具有优异的粘附铜特性的三元金属氮化硅，同时形成对铜的扩散的优异屏障。