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    DEPOSITION APPARATUS, DEPOSITION TARGET STRUCTURE, AND METHOD
    21.
    发明申请
    DEPOSITION APPARATUS, DEPOSITION TARGET STRUCTURE, AND METHOD 有权

    公开(公告)号：US20230069264A1

    公开(公告)日：2023-03-02

    申请号：US17461742

    申请日：2021-08-30

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chia-Hsi WANG ,  Yen-Yu CHEN

    IPC分类号： H01J37/34 ,  C23C14/34

    摘要： A deposition apparatus includes a process chamber, a wafer support in the process chamber, a backplane structure having a first surface in the process chamber facing the wafer support, a target having a second surface facing the first surface and a third surface facing the wafer support, and an adhesion structure in physical contact with the backplane structure and the target. The adhesion structure has an adhesion material layer, and a spacer embedded in the adhesion material layer.

    BARRIER LAYER FOR METAL INSULATOR METAL CAPACITORS
    24.
    发明申请
    BARRIER LAYER FOR METAL INSULATOR METAL CAPACITORS 有权

    公开(公告)号：US20210305356A1

    公开(公告)日：2021-09-30

    申请号：US16830981

    申请日：2020-03-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Anhao CHENG ,  Fang-Ting KUO ,  Yen-Yu CHEN

    IPC分类号： H01L49/02 ,  H01L23/528 ,  H01L23/522

    摘要： The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

    METROLOGY METHOD IN WAFER TRANSPORTATION
    27.
    发明申请
    METROLOGY METHOD IN WAFER TRANSPORTATION 审中-公开

    公开(公告)号：US20200251365A1

    公开(公告)日：2020-08-06

    申请号：US16857446

    申请日：2020-04-24

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Powen HUANG ,  Yao-Yuan SHANG ,  Kuo-Shu TSENG ,  Yen-Yu CHEN ,  Chun-Chih LIN ,  Yi-Ming DAI

    IPC分类号： H01L21/67 ,  H01L21/677 ,  H01L21/673 ,  H01L21/02 ,  G01D7/00 ,  G01D5/00

    摘要： A method for fault detection in a fabrication facility is provided. The method includes moving a wafer carrier along a predetermined path multiple times using a transportation apparatus. The method also includes collecting data associated with an environmental condition within the wafer carrier or around the wafer carrier using a metrology tool on the predetermined path in a previous movement of the transportation apparatus. The method further includes measuring the environmental condition within the wafer carrier or around the wafer carrier using the metrology tool during the movement of the wafer carrier. In addition, the method includes issuing a warning when the measured environmental condition is outside a range of acceptable values. The range of acceptable values is derived from the data collected in the previous movement of the transportation apparatus.

    SEMICONDUCTOR DEVICE WITH TUNABLE WORK FUNCTION
    28.
    发明申请
    SEMICONDUCTOR DEVICE WITH TUNABLE WORK FUNCTION 有权
    具有可调功能的半导体器件

    公开(公告)号：US20160225871A1

    公开(公告)日：2016-08-04

    申请号：US14609138

    申请日：2015-01-29

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chung-Liang CHENG ,  Wei-Jen CHEN ,  Yen-Yu CHEN ,  Wei ZHANG

    IPC分类号： H01L29/51 ,  H01L29/423

    CPC分类号： H01L27/092 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

    摘要： The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer and a silicide layer. The substrate has a trench. The gate dielectric multi-layer overlies the trench, in which the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %. The etch stop layer is disposed on the gate dielectric multi-layer. The work function metallic layer is disposed on the etch stop layer. The barrier layer is disposed on the work function metallic layer. The silicide layer is disposed on the barrier layer.

    摘要翻译： 金属氧化物半导体结构包括衬底，栅极电介质多层，蚀刻停止层，功函数金属层，阻挡层和硅化物层。 衬底具有沟槽。 栅极电介质多层覆盖沟槽，其中栅极电介质多层包括氟浓度基本上在1at％至10at％范围内的高k覆盖层。 蚀刻停止层设置在栅极电介质多层上。 功函数金属层设置在蚀刻停止层上。 阻挡层设置在功函数金属层上。 硅化物层设置在阻挡层上。

    PROCESS KIT OF PHYSICAL VAPOR DEPOSITION CHAMBER AND FABRICATING METHOD THEREOF
    29.
    发明申请
    PROCESS KIT OF PHYSICAL VAPOR DEPOSITION CHAMBER AND FABRICATING METHOD THEREOF 有权
    物理蒸气沉积室工艺套件及其制造方法

    公开(公告)号：US20150129414A1

    公开(公告)日：2015-05-14

    申请号：US14080561

    申请日：2013-11-14

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Shih-Wei BIH ,  Wei-Jen CHEN ,  Yen-Yu CHEN ,  Hsien-Chieh HSIAO ,  Chang-Sheng LEE ,  Wei-Chen LIAO ,  Wei ZHANG

    IPC分类号： H01J37/34 ,  C23C14/34

    CPC分类号： C23C14/34 ,  C23C14/564 ,  H01J37/32467 ,  H01J37/32477 ,  H01J37/34 ,  H01J37/3411 ,  H01J37/3426 ,  H01J37/3447

    摘要： A physical vapor deposition (PVD) chamber, a process kit of a PVD chamber and a method of fabricating a process kit of a PVD chamber are provided. In various embodiments, the PVD chamber includes a sputtering target, a power supply, a process kit, and a substrate support. The sputtering target has a sputtering surface that is in contact with a process region. The power supply is electrically connected to the sputtering target. The process kit has an inner surface at least partially enclosing the process region, and a liner layer disposed on the inner surface. The substrate support has a substrate receiving surface, wherein the liner layer disposed on the inner surface of the process kit has a surface roughness (Rz), and the surface roughness (Rz) is substantially in a range of 50-200 μm.

    摘要翻译： 提供物理气相沉积（PVD）室，PVD室的处理套件以及制造PVD室的处理套件的方法。 在各种实施例中，PVD室包括溅射靶，电源，处理套件和衬底支撑件。 溅射靶具有与工艺区域接触的溅射表面。 电源电连接到溅射靶。 处理套件具有至少部分地包围处理区域的内表面和设置在内表面上的衬垫层。 衬底支撑件具有衬底接收表面，其中设置在处理套件的内表面上的衬垫层具有表面粗糙度（Rz），并且表面粗糙度（Rz）基本上在50-200μm的范围内。

    SEMICONDUCTOR DEVICE HAVING WORK FUNCTION METAL STACK
    30.
    发明申请
    SEMICONDUCTOR DEVICE HAVING WORK FUNCTION METAL STACK 有权

    公开(公告)号：US20230109915A1

    公开(公告)日：2023-04-13

    申请号：US18066203

    申请日：2022-12-14

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Yen-Yu CHEN ,  Yu-Chi LU ,  Chih-Pin TSAO ,  Shih-Hsun CHANG

    IPC分类号： H01L21/28 ,  H01L29/49

    摘要： A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.