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    EFFICIENT IMPLEMENTATION OF CASCADED BIQUADS
    24.
    发明申请
    EFFICIENT IMPLEMENTATION OF CASCADED BIQUADS 审中-公开
    有效实施了CASCADED BIQUADS

    公开(公告)号：US20160112033A1

    公开(公告)日：2016-04-21

    申请号：US14515041

    申请日：2014-10-15

    Applicant: Texas Instruments Incorporated

    Inventor： Asheesh Bhardwaj ,  Lester A. Longley

    IPC: H03H17/02 ,  G06F17/10

    CPC classification number: G06F17/10 ,  H03H17/04 ,  H03H2017/0494

    Abstract: An improved biquad infinite impulse response filter is shown that may be implemented in a very large instruction word digital signal processor as well as in other processing circuitry. The new filter structure modifies the feedback path in the filter, resulting in a significant reduction in execution cycles.

    Abstract translation: 示出了可以在非常大的指令字数字信号处理器以及其它处理电路中实现的改进的双二阶无限脉冲响应滤波器。 新的滤波器结构修改滤波器中的反馈路径，导致执行周期的显着降低。

    MATRIX ACCELERATOR SYSTEM AND METHOD
    26.
    发明申请
    MATRIX ACCELERATOR SYSTEM AND METHOD 有权

    公开(公告)号：US20240411473A1

    公开(公告)日：2024-12-12

    申请号：US18813405

    申请日：2024-08-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arthur John Redfern ,  Asheesh Bhardwaj

    IPC: G06F3/06 ,  G06F15/00 ,  G06F17/16 ,  G06N3/045

    Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.

    ON-THE-FLY PADDING FOR CNN FEATURE MAPS
    27.
    发明公开
    ON-THE-FLY PADDING FOR CNN FEATURE MAPS 审中-公开

    公开(公告)号：US20240354003A1

    公开(公告)日：2024-10-24

    申请号：US18305871

    申请日：2023-04-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Asheesh Bhardwaj ,  William Leven ,  Varun Tripathi

    IPC: G06F3/06 ,  G06N3/0464

    CPC classification number: G06F3/0608 ,  G06F3/0646 ,  G06F3/0673 ,  G06N3/0464

    Abstract: Disclosed herein are systems and methods for providing on-the-fly padding to feature maps of convolutional neural networks (CNNs). In an implementation, a processor first identifies a padding schema for a feature map based on a type of convolution to be performed on the feature map. Next the processor identifies a feature vector from the feature map currently in an associated memory. Then, the processor determines a padding for the feature vector based on the padding schema. Finally, the processor applies the padding to the feature vector while the feature vector is transferred from the associated memory to registers of the suitable computer.

    ZERO PADDING FOR CONVOLUTIONAL NEURAL NETWORKS
    29.
    发明公开
    ZERO PADDING FOR CONVOLUTIONAL NEURAL NETWORKS 审中-公开

    公开(公告)号：US20240045922A1

    公开(公告)日：2024-02-08

    申请号：US17877882

    申请日：2022-07-30

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy David Anderson ,  Asheesh Bhardwaj ,  Burton Adrik Copeland

    IPC: G06F17/16 ,  G06F12/0813

    CPC classification number: G06F17/16 ,  G06F12/0813

    Abstract: In described examples, an integrated circuit (IC) includes a matrix multiplication accelerator including a first memory, a second memory, and a memory controller. The second memory is configured to store multiple rows of an input feature map on a single line of cells of the memory, and to store a filter kernel. The memory controller reads multiple contiguous memory vectors of the second memory, different ones of the contiguous memory vectors corresponding to different portions of the input feature map. The memory controller also replaces (with padding zeroes) values of respective ones of the contiguous memory vectors. The number and location of replaced values are selected in response to a column index of an element of the filter kernel in response to which the respective contiguous memory vector is read. Zero padded contiguous memory vectors are written to the first memory.

    PADDING AND SUPPRESSING ROWS AND COLUMNS OF DATA
    30.
    发明公开
    PADDING AND SUPPRESSING ROWS AND COLUMNS OF DATA 审中-公开

    公开(公告)号：US20230251970A1

    公开(公告)日：2023-08-10

    申请号：US18165196

    申请日：2023-02-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Asheesh Bhardwaj ,  Burton Adrik Copeland ,  Elliott Gurrola ,  Tim Anderson ,  William Leven

    IPC: G06F12/0837 ,  G06F12/0888

    CPC classification number: G06F12/0837 ,  G06F12/0888

    Abstract: A method is described herein. The method generally includes receiving stream parameters that defines an array, wherein the stream parameters include a first null element count and a second null element count. The method generally includes forming a stream of vectors for the multidimensional array responsive to the stream parameters. The stream of vectors generally includes a vector of null elements at a beginning of the stream of vectors based on the first null element count. The stream of vectors generally includes a null element at a beginning of each vector of the stream of vectors based on the second null element count. The stream of vectors generally includes a set of data distributed across a subset of the stream of vectors. The method generally includes providing the stream of vectors.

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