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    INTERCONNECT SINGULATION
    23.
    发明公开
    INTERCONNECT SINGULATION 审中-公开

    公开(公告)号：US20240194494A1

    公开(公告)日：2024-06-13

    申请号：US18582407

    申请日：2024-02-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chih-Chien Ho

    IPC: H01L21/48 ,  H01L21/66

    CPC classification number: H01L21/4842 ,  H01L22/20

    Abstract: A method for aligning interconnects that includes trimming and forming a frame of strips of interconnects. The frame of strips of interconnects includes interdigitated pins. The method also includes removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects. The method includes aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects. A strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects. The method further includes singulating the aligned array of strips of interconnects.

    Interconnect singulation
    25.
    发明授权
    Interconnect singulation 有权

    公开(公告)号：US11908705B2

    公开(公告)日：2024-02-20

    申请号：US17504148

    申请日：2021-10-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chih-Chien Ho

    IPC: H01L21/48 ,  H01L21/66

    CPC classification number: H01L21/4842 ,  H01L22/20

    Abstract: A method for aligning interconnects that includes trimming and forming a frame of strips of interconnects. The frame of strips of interconnects includes interdigitated pins. The method also includes removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects. The method includes aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects. A strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects. The method further includes singulating the aligned array of strips of interconnects.

    Electronic device with three dimensional thermal pad
    28.
    发明授权
    Electronic device with three dimensional thermal pad 有权

    公开(公告)号：US11081428B2

    公开(公告)日：2021-08-03

    申请号：US16537535

    申请日：2019-08-10

    Applicant: Texas Instruments Incorporated

    Inventor： Stanley Chou ,  Yuh-Harng Chien ,  Steven Alfred Kummerl ,  Bo-Hsun Pan ,  Pi-Chiang Huang ,  Frank Yu ,  Chih-Chien Ho

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/492

    Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.

    Leadframe
    29.
    发明授权
    Leadframe 有权

    公开(公告)号：US10573581B2

    公开(公告)日：2020-02-25

    申请号：US15280398

    申请日：2016-09-29

    Applicant: Texas Instruments Incorporated

    Inventor： Chih-Chien Ho ,  Chung-Hao Lin ,  Yuh-Harng Chien

    IPC: H01L23/495

    Abstract: A leadframe has a peripheral frame. A die attach pad (DAP) is positioned inwardly and downwardly of the peripheral frame. Two spaced apart parallel arms engage one side of the DAP. In one embodiment the arms are portions of a U-shaped strap.

    Packaged semiconductor device having multi-level leadframes configured as modules
    30.
    发明授权
    Packaged semiconductor device having multi-level leadframes configured as modules 有权

    公开(公告)号：US10211132B2

    公开(公告)日：2019-02-19

    申请号：US15924767

    申请日：2018-03-19

    Applicant: Texas Instruments Incorporated

    Inventor： Chia-Yu Chang ,  Chih-Chien Ho ,  Steven Su

    IPC: H01L23/495 ,  H01L21/00 ,  H05K7/18 ,  H01L23/31 ,  H01L23/13 ,  H01L23/00

    Abstract: A leadframe (100) comprises a frame (101) of sheet metal in a first planar level, where the frame has metallic leads (110) and a first metallic pad (120) extending inward from the frame, and the first pad is tied to the frame by first metallic straps (120a). The leadframe further has a second metallic pad (130) in a second planar level parallel to and spaced from the first level, where the second pad is tied by second metallic straps (132) to the frame. In addition, the leadframe has a third metallic pad (140) in a third planar level parallel to and spaced from the second level and additively from the first level, where the third pad is tied by third metallic straps (131) to the second pad.

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