公开(公告)号：US20190243647A1

公开(公告)日：2019-08-08

申请号：US16384434

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Joseph ZBICIAK ,  Kai CHIRCA

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

公开(公告)号：US20240220258A1

公开(公告)日：2024-07-04

申请号：US18607703

申请日：2024-03-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph ZBICIAK

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/30149 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/3016 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/383 ,  G06F12/0875 ,  G06F2212/452

Abstract: A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.

公开(公告)号：US20220350542A1

公开(公告)日：2022-11-03

申请号：US17867134

申请日：2022-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR ,  Alan DAVIS

IPC: G06F3/06 ,  G06F9/30

Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

公开(公告)号：US20220269607A1

公开(公告)日：2022-08-25

申请号：US17740811

申请日：2022-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Matthew David PIERSON ,  Timothy David ANDERSON ,  Joseph ZBICIAK

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F3/06 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

Abstract: A device includes an interconnect and a plurality of devices connected to the interconnect. The plurality of devices includes a first interface connected to the interconnect and a second interface connected to the interconnect. The plurality of devices further includes a first memory bank connected to the interconnect and a second memory bank connected to the interconnect. The plurality of devices further includes an external memory interface connected to the interconnect and a controller configured to establish virtual channels among the plurality of devices connected to the interconnect.

公开(公告)号：US20220129403A1

公开(公告)日：2022-04-28

申请号：US17571612

申请日：2022-01-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera BALASUBRAMANIAN ,  Joseph ZBICIAK ,  Sureshkumar GOVINDARAJ

IPC: G06F13/42 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F12/0875 ,  G06F15/76

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

公开(公告)号：US20210357226A1

公开(公告)日：2021-11-18

申请号：US17387450

申请日：2021-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Kai CHIRCA

IPC: G06F9/30

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

公开(公告)号：US20200371795A1

公开(公告)日：2020-11-26

申请号：US16422719

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph ZBICIAK ,  Dheera Balasubramanian SAMUDRALA ,  Duc BUI

IPC: G06F9/30 ,  G06F7/78

Abstract: A method to transpose source data in a processor in response to a vector bit transpose instruction includes specifying, in respective fields of the vector bit transpose instruction, a source register containing the source data and a destination register to store transposed data. The method also includes executing the vector bit transpose instruction by interpreting N×N bits of the source data as a two-dimensional array having N rows and N columns, creating transposed source data by transposing the bits by reversing a row index and a column index for each bit, and storing the transposed source data in the destination register.

公开(公告)号：US20200371789A1

公开(公告)日：2020-11-26

申请号：US16422324

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Sahithi KRISHNA ,  Soujanya NARNUR

IPC: G06F9/30 ,  G06F12/0811

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US20190243648A1

公开(公告)日：2019-08-08

申请号：US16384537

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. ANDERSON ,  Joseph ZBICIAK ,  Duc BUI ,  Mel Alan PHIPPS ,  Todd T. HAHN

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.