公开(公告)号：US20180045778A1

公开(公告)日：2018-02-15

申请号：US15722975

申请日：2017-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rajesh Mittal ,  Rajat Mehrotra

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/31713 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318572

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

公开(公告)号：US09823282B2

公开(公告)日：2017-11-21

申请号：US14735223

申请日：2015-06-10

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Sudhir Polarouthu

IPC: G01R19/25 ,  G01R31/30 ,  G01R19/257 ,  G01R31/3185 ,  G01R31/3181

CPC classification number: G01R19/257 ,  G01R31/3004 ,  G01R31/3181 ,  G01R31/318516

Abstract: An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; and an electronic monitoring circuit (100) that has a variably operable reference circuit (150) responsive to an input register (155) and having an output, comparison circuitry (110) having plural outputs and having a first input coupled to the output of said variably operable reference circuit (150) and a set of second inputs each second input coupled to a respective one of said power grid points (30.i); and an output register (120) having at least two register bit cells (120.i) respectively fed by the plural outputs of said comparison circuitry (110.i). Other integrated circuits, and processes of testing and of manufacturing are also disclosed.

公开(公告)号：US20140208177A1

公开(公告)日：2014-07-24

申请号：US13749623

申请日：2013-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rubin Ajit Parekhji ,  Srivaths Ravi ,  Prakash Narayanan ,  Milan Shetty

IPC: G01R31/3177

CPC classification number: G01R31/318544 ,  G01R31/318572

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract translation: 公开了一种测试被测设备（DUT）和测试系统的方法。 该方法包括生成与从测试系统接收的测试图案结构相关联的至少一个控制信号。 该方法进一步包括从DUT中的M个I / O端口中选择M1个端口，以基于控制信号接收与测试模式结构相对应的扫描输入，从M个I / O端口中选择M2个端口 以提供基于控制信号的扫描输出，其中M1和M2中的每一个是从0到M中选择的数字，并且其中M1和M2的和小于或等于M.此后，该方法包括执行扫描测试 基于提供给M1端口的扫描输入并从M2端口接收扫描输出的DUT的DUT。

公开(公告)号：US11879940B2

公开(公告)日：2024-01-23

申请号：US17355386

申请日：2021-06-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Prakash Narayanan

IPC: G01R31/3177 ,  G01R31/317 ,  G11C29/56 ,  G06F11/10 ,  G11C29/36 ,  G11C29/42

CPC classification number: G01R31/3177 ,  G01R31/31718 ,  G01R31/31724 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/36 ,  G11C29/42 ,  G11C29/56004 ,  G11C2029/3602 ,  G11C2029/5602

Abstract: A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.

公开(公告)号：US11592483B2

公开(公告)日：2023-02-28

申请号：US17396079

申请日：2021-08-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin A Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G01R31/00 ,  G01R31/3177 ,  G01R31/3185

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US20220358230A1

公开(公告)日：2022-11-10

申请号：US17354777

申请日：2021-06-22

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Nikita Naresh

IPC: G06F21/62 ,  G06F21/74 ,  G06F15/78

Abstract: Methods and apparatus are disclosed to protect secure assets using scan operations. One example apparatus includes logic circuitry including a scan chain that includes data storage elements and design logic coupled to the scan chain. The example apparatus also includes data storage to store secure data. The design logic is coupled to the data storage. The example apparatus also includes a security controller to transition the apparatus out of a secure mode of operation. The transition includes the security controller to cause the scan chain to serially shift secure scan data from an input of the scan chain into each data storage element of the data storage elements of the scan chain.

公开(公告)号：US10776546B2

公开(公告)日：2020-09-15

申请号：US16410391

申请日：2019-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Prakash Narayanan ,  Saket Jalan

IPC: G06F17/50 ,  G01R27/28 ,  G01R31/28 ,  G01R31/36 ,  G06G7/62 ,  G06F30/3312 ,  G06F30/30 ,  G06F30/398 ,  H01L23/58 ,  H01L25/00 ,  H01L29/10 ,  H03K19/00 ,  G06F30/392 ,  G06F30/394

Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

公开(公告)号：US20200174069A1

公开(公告)日：2020-06-04

申请号：US16780119

申请日：2020-02-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G01R31/3177 ,  G01R31/3185

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US10591540B2

公开(公告)日：2020-03-17

申请号：US15925200

申请日：2018-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G06F11/00 ,  G01R31/3177 ,  G01R31/3185

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US20190235020A1

公开(公告)日：2019-08-01

申请号：US16380182

申请日：2019-04-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rajesh Kumar Mittal ,  Rajat Mehrotra

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/31713 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318572

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.