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    EXIT HISTORY BASED BRANCH PREDICTION
    21.
    发明申请
    EXIT HISTORY BASED BRANCH PREDICTION 有权

    公开(公告)号：US20220326954A1

    公开(公告)日：2022-10-13

    申请号：US17849994

    申请日：2022-06-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  David E. Smith, JR. ,  Paul D. Gauvreau

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A computer-implemented method includes fetching a fetch-packet containing a first hyper-block from a first address of a memory, the fetch-packet containing a bitwise distance from an entry point of the first hyper-block to a predicted exit point; executing a first branch instruction of the first hyper-block, wherein the first branch instruction corresponds to a first exit point, and wherein the first branch instruction includes an address corresponding to an entry point of a second hyper-block; storing, responsive to executing the first branch instruction, a bitwise distance from the entry point of the first hyper-block to the first exit point; and moving a program counter from the first exit point of the first hyper-block to the entry point of the second hyper-block.

    Entering protected pipeline mode without annulling pending instructions
    22.
    发明授权
    Entering protected pipeline mode without annulling pending instructions 有权

    公开(公告)号：US11029997B2

    公开(公告)日：2021-06-08

    申请号：US16384484

    申请日：2019-04-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Duc Bui ,  Timothy D. Anderson

    IPC: G06F9/312 ,  G06F9/48 ,  G06F9/38 ,  G06F9/30

    Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.

    Mechanism for interrupting and resuming execution on an unprotected pipeline processor
    23.
    发明授权
    Mechanism for interrupting and resuming execution on an unprotected pipeline processor 有权

    公开(公告)号：US10990398B2

    公开(公告)日：2021-04-27

    申请号：US16384434

    申请日：2019-04-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Kai Chirca

    IPC: G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F9/30 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F9/345

    Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

    OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION
    27.
    发明申请
    OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION 审中-公开
    用于不及格相关交易完成的可选确认

    公开(公告)号：US20150370710A1

    公开(公告)日：2015-12-24

    申请号：US14841956

    申请日：2015-09-01

    Applicant: Texas Instruments Incorporated

    Inventor： Daniel B. Wu ,  Matthew D. Pierson ,  Kai Chirca ,  Timothy D. Anderson

    IPC: G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

    Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

    Faster and More Efficient Different Precision Sum of Absolute Differences for Dynamically Configurable Block Searches for Motion Estimation
    28.
    发明申请
    Faster and More Efficient Different Precision Sum of Absolute Differences for Dynamically Configurable Block Searches for Motion Estimation 有权
    更快，更高效的动态可配置块搜索的绝对差异精度和的运动估计

    公开(公告)号：US20150082004A1

    公开(公告)日：2015-03-19

    申请号：US14327002

    申请日：2014-07-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

    IPC: G06F9/30

    CPC classification number: H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

    Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

    Abstract translation: 本发明是在单个操作中形成多个绝对值（SAD）的数字信号处理器。 执行包括两组多行的绝对值操作之和的操作单元，每行产生SAD输出。 多个绝对值差分单元接收相应的压缩候选像素数据和压缩参考像素数据。 行夏天对行中的绝对值差单位的输出求和。 候选像素相对于参考像素相对于一组行中的每个后续行偏移一个像素。 两组行在包含在指令指定操作数中的候选像素的相对的两半上进行操作。 可以使用绝对差分单位和行夏季的进位链控制在不同的数据宽度上执行SAD操作。

    CPUs with capture queues to save and restore intermediate results and out-of-order results
    29.
    发明授权
    CPUs with capture queues to save and restore intermediate results and out-of-order results 有权

    公开(公告)号：US12223327B2

    公开(公告)日：2025-02-11

    申请号：US18487186

    申请日：2023-10-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. Anderson ,  Duc Bui ,  Joseph Zbiciak ,  Reid E. Tatge

    IPC: G06F9/38

    Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

    Exit history based branch prediction
    30.
    发明授权
    Exit history based branch prediction 有权

    公开(公告)号：US12197917B2

    公开(公告)日：2025-01-14

    申请号：US17849994

    申请日：2022-06-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  David E. Smith, Jr. ,  Paul D. Gauvreau

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A computer-implemented method includes fetching a fetch-packet containing a first hyper-block from a first address of a memory. The fetch-packet contains a bitwise distance from an entry point of the first hyper-block to a predicted exit point. A first branch instruction of the first hyper-block is executed that corresponds to a first exit point. The first branch instruction includes an address corresponding to an entry point of a second hyper-block. Responsive to executing the first branch instruction, a bitwise distance from the entry point of the first hyper-block to the first exit point is stored. A program counter is moved from the first exit point of the first hyper-block to the entry point of the second hyper-block.

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