公开(公告)号：US09941296B2

公开(公告)日：2018-04-10

申请号：US15424532

申请日：2017-02-03

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L29/76 ,  H01L27/11582 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L21/265 ,  H01L21/223

CPC classification number: H01L27/11582 ,  H01L21/223 ,  H01L21/265 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US20210210507A1

公开(公告)日：2021-07-08

申请号：US17205329

申请日：2021-03-18

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaaki HIGUCHI ,  Masaru Kito ,  Masao Shingu

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/66 ,  H01L29/792

Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.

公开(公告)号：US10971515B2

公开(公告)日：2021-04-06

申请号：US16293954

申请日：2019-03-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shigeki Kobayashi ,  Masaru Kito ,  Yasuhiro Uchiyama

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10 ,  H01L27/11573 ,  H01L23/528 ,  H01L29/40 ,  H01L29/04 ,  H01L29/167 ,  H01L29/51 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/28

Abstract: A semiconductor memory device includes: a first conductive layer and a first insulating layer extending in a first direction, these layers being arranged in a second direction intersecting the first direction; a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first and second directions; a second semiconductor layer opposed to the first conductive layer, extending in the third direction; a first contact electrode connected to the first semiconductor layer; and a second contact electrode connected to the second semiconductor layer. In a first cross section extending in the first and second directions, an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer, and an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.

公开(公告)号：USRE48191E1

公开(公告)日：2020-09-01

申请号：US15890143

申请日：2018-02-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: G11C11/14 ,  H01L27/11578 ,  G11C16/04 ,  G11C16/06 ,  H01L27/11565 ,  H01L27/11582

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

公开(公告)号：US20200243560A1

公开(公告)日：2020-07-30

申请号：US16849457

申请日：2020-04-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/49 ,  H01L29/423 ,  H01L29/16 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/223 ,  H01L27/11578 ,  H01L29/792

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US10418378B2

公开(公告)日：2019-09-17

申请号：US15915653

申请日：2018-03-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US10347648B2

公开(公告)日：2019-07-09

申请号：US15883730

申请日：2018-01-30

Applicant: Toshiba Memory Corporation

Inventor： Naoki Yasuda ,  Masaru Kito

IPC: H01L27/115 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51 ,  H01L27/11568 ,  H01L27/11573

Abstract: A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film includes a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.

公开(公告)号：US20190096908A1

公开(公告)日：2019-03-28

申请号：US16204444

申请日：2018-11-29

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC: H01L27/11582 ,  H01L27/11578 ,  G11C16/04 ,  H01L27/105 ,  H01L29/51 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11551

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：USRE46957E1

公开(公告)日：2018-07-17

申请号：US14296237

申请日：2014-06-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshimasa Mikajiri ,  Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota

IPC: G11C16/04 ,  H01L29/792 ,  H01L27/11573 ,  H01L27/11578 ,  G11C5/02 ,  H01L27/11556

CPC classification number: G11C16/0466 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

Abstract: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.

公开(公告)号：USRE46785E1

公开(公告)日：2018-04-10

申请号：US14992650

申请日：2016-01-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: G11C11/14 ,  H01L27/11578 ,  G11C16/06 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11565

CPC classification number: H01L27/11578 ,  G11C16/0466 ,  G11C16/06 ,  H01L27/11565 ,  H01L27/11582

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.