公开(公告)号：US20130001591A1

公开(公告)日：2013-01-03

申请号：US13174170

申请日：2011-06-30

申请人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Yao-Tsung Huang ,  Clement Hsingjen Wann

发明人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Yao-Tsung Huang ,  Clement Hsingjen Wann

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/24 ,  H01L29/26

CPC分类号： H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/785

摘要： An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures.

摘要翻译： 公开了一种集成电路器件及其制造方法。 示例性器件包括具有衬底表面的半导体衬底和设置在半导体衬底中的用于隔离器件的NMOS区域和器件的PMOS区域的沟槽隔离结构。 该器件还包括第一鳍结构，其包括设置在具有高带隙能量和晶格常数大于Ge的III-V半导体材料的层上的硅或SiGe; 包括硅或SiGe的第二鳍结构，其设置在具有高带隙能量和比Ge小的晶格常数的III-V半导体材料层上; 以及设置在垂直于第一和第二鳍结构并且布置在其上的栅极结构。

公开(公告)号：US08253167B2

公开(公告)日：2012-08-28

申请号：US12694002

申请日：2010-01-26

申请人： Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

发明人： Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC分类号： H01L27/092

CPC分类号： H01L29/205 ,  B82Y10/00 ,  H01L21/8252 ,  H01L27/085 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/122 ,  H01L29/42316 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7783

摘要： An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

摘要翻译： 集成电路结构包括基板和第一和第二多个III-V半导体层。 所述第一多个III-V半导体层包括在所述衬底上的第一底部阻挡层; 在第一底部屏障上的第一通道层; 以及第一通道层上的第一顶部势垒。 第一场效应晶体管（FET）包括第一沟道区，其包括第一沟道层的一部分。 第二多个III-V半导体层在第一多个III-V半导体层之上，并且包括第二底部屏障; 在第二底部屏障上的第二通道层; 以及在第二通道层上的第二顶部阻挡层。 第二FET包括第二沟道区，其包括第二沟道层的一部分。

公开(公告)号：US20110306179A1

公开(公告)日：2011-12-15

申请号：US12814088

申请日：2010-06-11

申请人： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

发明人： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC分类号： H01L21/76 ,  C23C16/02 ,  C30B25/10

CPC分类号： H01L21/0262 ,  C30B25/105 ,  C30B25/186 ,  C30B29/40 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/76224

摘要： A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).

摘要翻译： 一种器件包括提供硅衬底; 在高于约900℃的第一温度下退火硅衬底; 以及将所述硅衬底的温度从所述第一温度降低到第二温度。 在降低温度的步骤期间的降温速率大于约1℃/秒。 使用金属有机化学气相沉积（MOCVD）在硅衬底的表面上外延生长III-V族化合物半导体区域。

公开(公告)号：US09601594B2

公开(公告)日：2017-03-21

申请号：US13295178

申请日：2011-11-14

申请人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/70 ,  H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/762

CPC分类号： H01L29/0847 ,  H01L21/76224 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.

公开(公告)号：US08815712B2

公开(公告)日：2014-08-26

申请号：US13414357

申请日：2012-03-07

申请人： Cheng-Tien Wan ,  You-Ru Lin ,  Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Tien Wan ,  You-Ru Lin ,  Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/36 ,  H01L21/20

CPC分类号： H01L21/3065 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02658 ,  H01L29/66636 ,  H01L29/78

摘要： A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.

摘要翻译： 在第一半导体区域的表面上进行处理，其中使用包括含氧气体和用于蚀刻半导体材料的蚀刻气体的处理气体进行处理。 进行外延以在第一半导体区域的表面上生长第二半导体区域。

公开(公告)号：US08759203B2

公开(公告)日：2014-06-24

申请号：US12842221

申请日：2010-07-23

申请人： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

发明人： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC分类号： H01L21/20

CPC分类号： H01L21/02647 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02617 ,  H01L21/02639

摘要： A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.

摘要翻译： 形成集成电路结构的方法包括在衬底的至少一部分上形成绝缘层; 在所述绝缘层的顶表面上形成多个半导体柱。 多个半导体柱由绝缘层的一部分水平隔开。 以周期性图案分配多个半导体柱。 该方法还包括从半导体柱的顶表面和侧壁外延生长III-V族化合物半导体膜。

公开(公告)号：US20130171792A1

公开(公告)日：2013-07-04

申请号：US13414357

申请日：2012-03-07

申请人： Cheng-Tien Wan ,  You-Ru Lin ,  Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Tien Wan ,  You-Ru Lin ,  Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/762 ,  H01L21/336

CPC分类号： H01L21/3065 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02658 ,  H01L29/66636 ,  H01L29/78

摘要： A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.

摘要翻译： 在第一半导体区域的表面上进行处理，其中使用包括含氧气体和用于蚀刻半导体材料的蚀刻气体的处理气体进行处理。 进行外延以在第一半导体区域的表面上生长第二半导体区域。

公开(公告)号：US20120329254A1

公开(公告)日：2012-12-27

申请号：US13595797

申请日：2012-08-27

申请人： Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

发明人： Heng-Kuang Lin ,  Pei-Chin Chiu ,  Jen-Inn Chyi ,  Han-Chieh Ho ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC分类号： H01L21/20

CPC分类号： H01L29/205 ,  B82Y10/00 ,  H01L21/8252 ,  H01L27/085 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/122 ,  H01L29/42316 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/7783

摘要： An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

摘要翻译： 集成电路结构包括基板和第一和第二多个III-V半导体层。 所述第一多个III-V半导体层包括在所述衬底上的第一底部阻挡层; 在第一底部屏障上的第一通道层; 以及第一通道层上的第一顶部势垒。 第一场效应晶体管（FET）包括第一沟道区，其包括第一沟道层的一部分。 第二多个III-V半导体层在第一多个III-V半导体层之上，并且包括第二底部屏障; 在第二底部屏障上的第二通道层; 以及在第二通道层上的第二顶部阻挡层。 第二FET包括第二沟道区，其包括第二沟道层的一部分。

公开(公告)号：US08183134B2

公开(公告)日：2012-05-22

申请号：US13009151

申请日：2011-01-19

申请人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

发明人： Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/8258 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02667 ,  H01L21/02675

摘要： Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.

摘要翻译： 通过在沟槽中外延生长III-V族化合物半导体区域，然后对该区域进行封盖和退火来减少或消除堆叠故障。 封盖层限制了原子从该区域的逃逸，并且能够与退火一起减少或消除堆垛层错。

公开(公告)号：US20120025201A1

公开(公告)日：2012-02-02

申请号：US12847877

申请日：2010-07-30

申请人： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

发明人： Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Cheng-Hsien Wu

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L21/76283 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/76224 ,  H01L21/76272 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/2003

摘要： A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.

摘要翻译： 提供具有外延层的半导体器件的制造方法。 半导体器件具有形成在其中的沟槽的衬底和形成在沟槽下方的凹部。 凹槽具有（111）晶体取向的侧壁。 沟槽的深度使得深度大于或等于凹部的侧壁长度的二分之一。 在凹槽和沟槽中形成外延层。 沟槽的深度足以引起在半导体衬底和外延层的界面之间形成的位错，从而沿沟槽的侧壁终止。