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    Dynamic type semiconductor memory device having reduced peak current during refresh mode and method of operating the same
    21.
    发明授权
    Dynamic type semiconductor memory device having reduced peak current during refresh mode and method of operating the same 失效
    在刷新模式期间具有降低的峰值电流的动态类型半导体存储器件及其操作方法

    公开(公告)号：US5367493A

    公开(公告)日：1994-11-22

    申请号：US892897

    申请日：1992-06-03

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/406 ,  G11C11/4091 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C11/4091

    摘要： A dynamic type semiconductor memory device includes a pair of transistors provided in a signal line for transmitting a sense amplifier drive signal to sense amplifiers. The transistors of the pair are provided in parallel with each other, and are activated to couple the sense amplifiers to a source of generating the sense amplifier drive signal. One of the pair of transistors is made nonconductive in a refresh mode of operation. This arrangement reduces the peak value of a current for charging and/or discharging bit lines by the sense amplifiers in the refresh mode of operation, and reduces a noise on a power source line or a ground line at an on-board level, resulting in stable operation of a system.

    摘要翻译： 动态型半导体存储器件包括设置在用于将读出放大器驱动信号传输到读出放大器的信号线中的一对晶体管。 该对的晶体管彼此并联设置，并且被激活以将感测放大器耦合到产生读出放大器驱动信号的源极。 一对晶体管中的一个在刷新操作模式下变得不导通。 这种布置降低了在刷新操作模式下由读出放大器对位线进行充电和/或放电的电流的峰值，并降低了板载电平上的电源线或接地线上的噪声，导致 稳定运行的系统。

    Input circuit of a semiconductor device
    22.
    发明授权
    Input circuit of a semiconductor device 失效
    半导体器件的输入电路

    公开(公告)号：US5208474A

    公开(公告)日：1993-05-04

    申请号：US646544

    申请日：1991-01-28

    申请人： Tadato Yamagata ,  Hiroshi Miyamoto ,  Michihiro Yamada

    发明人： Tadato Yamagata ,  Hiroshi Miyamoto ,  Michihiro Yamada

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/0251

    摘要： An input circuit of a semiconductor device includes a P type well formed on the main surface of a semiconductor substrate, and an N type region formed on the main surface in the P type well. A P-N junction is formed by the N type region and the P type well. An input voltage is applied to the N type region, which input voltage is applied to an internal circuit formed on the semiconductor substrate. When the P-N junction is rendered conductive by an application of an excessive voltage to the input voltage, the current caused by the excessive voltage is absorbed to the supply potential through the P type region formed in the P well.

    摘要翻译： 半导体器件的输入电路包括在半导体衬底的主表面上良好地形成的P型阱和形成在P型阱的主表面上的N型区域。 由N型区域和P型阱形成P-N结。 输入电压施加到N型区域，该输入电压被施加到形成在半导体衬底上的内部电路。 当通过对输入电压施加过大的电压使P-N结导通时，由过电压引起的电流通过形成在P阱中的P型区域吸收到电源电位。

    Integrated circuit having superconductive wirings
    23.
    发明授权
    Integrated circuit having superconductive wirings 失效
    集成电路具有超导布线

    公开(公告)号：US5083188A

    公开(公告)日：1992-01-21

    申请号：US618024

    申请日：1990-11-27

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： H01L39/06 ,  H01L21/3205 ,  H01L23/36 ,  H01L23/52 ,  H01L23/532

    CPC分类号： H01L23/36 ,  H01L23/53285 ,  H01L2924/0002 ,  Y10S505/703 ,  Y10S505/704 ,  Y10S505/856 ,  Y10S505/887

    摘要： An integrated circuit having a superconductive wiring comprises a semiconductor substrate, an integrated circuit device formed on the semiconductor substrate and a wiring connected to the integrated circuit device. The wiring is formed of a superconductive material and has a wide portion for heat radiation. The manufacturing method of the same comprises the steps of preparing a semiconductor substrate, forming an integrated circuit device on the semiconductor substrate, and connecting a wiring having a wide portion for heat radiation and formed of a superconductive material to the integrated circuit device on the semiconductor substrate.

    摘要翻译： 具有超导布线的集成电路包括半导体衬底，形成在半导体衬底上的集成电路器件和连接到集成电路器件的布线。 布线由超导材料形成，并且具有用于散热的宽部分。 其制造方法包括以下步骤：制备半导体衬底，在半导体衬底上形成集成电路器件，并将具有用于散热的宽部分并由超导材料形成的布线连接到半导体上的集成电路器件 基质。

    Semiconductor memory device with logic level responsive testing circuit and method therefor
    24.
    发明授权
    Semiconductor memory device with logic level responsive testing circuit and method therefor 失效
    具有逻辑电平响应测试电路的半导体存储器件及其方法

    公开(公告)号：US5016220A

    公开(公告)日：1991-05-14

    申请号：US441005

    申请日：1989-11-27

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C29/34 ,  G11C29/36 ,  G11C29/38

    CPC分类号： G11C29/36 ,  G11C29/38

    摘要： A testing circuit for a semiconductor memory device is provided. An AND operation is performed on the data read out from each block of a memory cell array when the bit data written into each block of the memory cell array for testing is "1", and a NOR operation is performed on the data read out from each block of the memory cell array when the bit data written into each block of the memory cell array is "0". In this manner, even when the data read out from the blocks are all inverted in their logical states through error, such error can be detected.

    摘要翻译： 提供了一种用于半导体存储器件的测试电路。 当写入用于测试的存储单元阵列的每个块的位数据为“1”时，对从存储单元阵列的每个块读出的数据进行AND运算，并且对从 当写入存储单元阵列的每个块的位数据为“0”时，存储单元阵列的每个块。 以这种方式，即使从块读出的数据通过错误全部以逻辑状态反转，也可以检测出这种错误。

    Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system
    26.
    再颁专利
    Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system 有权
    半导体集成电路器件包括具有集成到单个芯片中的命令解码系统和逻辑电路的RAM以及具有命令解码系统的RAM的测试方法

    公开(公告)号：USRE39579E1

    公开(公告)日：2007-04-17

    申请号：US09871978

    申请日：2001-06-04

    申请人： Makoto Hatakenaka ,  Akira Yamazaki ,  Shigeki Tomishima ,  Tadato Yamagata

    发明人： Makoto Hatakenaka ,  Akira Yamazaki ,  Shigeki Tomishima ,  Tadato Yamagata

    IPC分类号： G06F11/00

    CPC分类号： G06F11/00

    摘要： A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector and are provided to the core unit of the synchronous dynamic random access memory for testing.

    摘要翻译： 半导体集成电路器件包括集成在单个半导体芯片上的逻辑电路和包括核心单元的同步动态随机存取存储器。 半导体集成电路装置包括：同步动态随机存取存储器控制电路，其从逻辑电路接收用于同步动态随机存取存储器的外部控制信号，并将内部控制信号输出到同步动态随机存取存储器的核心单元。 对于半导体集成电路器件的测试，通过外部端子提供外部测试信号。 外部测试信号由选择器选择，并提供给同步动态随机存取存储器的核心单元进行测试。

    Data bus
    27.
    发明授权
    Data bus 失效
    数据总线

    公开(公告)号：US06844754B2

    公开(公告)日：2005-01-18

    申请号：US10299712

    申请日：2002-11-20

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C11/409 ,  H03K19/0175 ,  H03K19/003

    CPC分类号： G11C7/10

    摘要： In a memory system having a data bus transferring data in either direction, highly reliable data transfer is provided regardless of the direction in which data is transferred. The signal lines of a data bus (12) bidirectionally transfer data. That is to say, during data write operations to a DIMM, the signal lines transfer data from a memory controller (10) to the DIMM, and during data read operations, they transfer data from the DIMM to the memory controller (10). The signal lines have, as terminating resistors, terminating variable resistors (VRt) whose impedance is controlled by the memory controller (10). During data write operations to the DIMM, the memory controller (10) sets the impedance of each terminating variable resistor (VRt) at a value suitable for writing, and during data read operations, it sets the impedance of each terminating variable resistor (VRt) at a value suitable for reading.

    摘要翻译： 在具有在任一方向上传送数据的数据总线的存储器系统中，无论数据传送的方向如何，都提供高可靠性的数据传输。 数据总线（12）的信号线双向传输数据。 也就是说，在对DIMM的数据写入操作期间，信号线将数据从存储器控制器（10）传送到DIMM，并且在数据读取操作期间，它们将数据从DIMM传送到存储器控制器（10）。 信号线具有作为终端电阻器的端接可变电阻器（VRt），其阻抗由存储器控制器（10）控制。 在对DIMM的数据写入操作期间，存储器控制器（10）将每个终端可变电阻器（VRt）的阻抗设置为适合于写入的值，并且在数据读取操作期间，它设置每个端接可变电阻器（VRt）的阻抗， 以适合阅读的价值。

    Semiconductor memory module and register buffer device for use in the same
    28.
    发明授权
    Semiconductor memory module and register buffer device for use in the same 有权
    半导体存储器模块和寄存器缓冲器用于使用

    公开(公告)号：US06650588B2

    公开(公告)日：2003-11-18

    申请号：US10178537

    申请日：2002-06-25

    申请人： Tadato Yamagata

    发明人： Tadato Yamagata

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/406 ,  G11C11/4093

    摘要： In a semiconductor memory module having a plurality of DRAMs, when an input command is detected as a refresh command according to external control signals externally input for command-execution to a register buffer, internal control signals for a partial number of the DRAMs preliminarily selected among the plurality of DRAMs are delayed. Thus, the refresh command is executed with a time difference, and the semiconductor memory module prevents the plurality of dynamic semiconductor memories from simultaneously entering refresh modes to cause a great peak current to flow, and thereby implementing a stable operation.

    摘要翻译： 在具有多个DRAM的半导体存储器模块中，当根据从外部输入的用于命令执行的寄存器缓冲器的外部控制信号将输入命令检测为刷新命令时，预先选择的DRAM的部分数量的内部控制信号 多个DRAM被延迟。 因此，以时间差执行刷新命令，并且半导体存储器模块防止多个动态半导体存储器同时进入刷新模式以导致大的峰值电流流动，从而实现稳定的操作。