公开(公告)号：US20170250282A1

公开(公告)日：2017-08-31

申请号：US15054133

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yu-Ting Lin ,  Po-Kai Hsiao ,  Po-Kang Ho ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545

Abstract: A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality of semiconductor fins. The isolation structures are located on the substrate to isolate the semiconductor fins. In addition, the semiconductor fins protrude from the isolation structures. The blocking layers are located between the isolation structures and the semiconductor fins. The material of the blocking layers is different from the material of the isolation structures. The gate stack is disposed across portions of the semiconductor fins, portions of the blocking layers and portions of the isolation structures. In addition, a method for fabricating the FinFET is also provided.

公开(公告)号：US20170243903A1

公开(公告)日：2017-08-24

申请号：US15590264

申请日：2017-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Fann Ting ,  Chih-Yu Lai ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ching-Chun Wang

IPC: H01L27/146

CPC classification number: H01L27/146 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14683

Abstract: The present disclosure relates to a semiconductor image sensor device. In some embodiments, the semiconductor image sensor device includes a semiconductor substrate having a first surface configured to receive incident radiation. A plurality of sensor elements are arranged within the semiconductor substrate. A first charged layer is arranged on an entirety of a second surface of the semiconductor substrate facing an opposite direction as the first surface. The second surface is between the first charged layer and the first surface of the semiconductor substrate.

公开(公告)号：US11551979B2

公开(公告)日：2023-01-10

申请号：US17079044

申请日：2020-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Cheng Chou ,  Shiu-Ko Jangjian ,  Cheng-Ta Wu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L21/324 ,  H01L27/088

Abstract: A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.

公开(公告)号：US11011641B2

公开(公告)日：2021-05-18

申请号：US16735495

申请日：2020-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Cheng-Wei Chen ,  Shiu-Ko Jangjian ,  Ting-Chun Wang

IPC: H01L27/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

公开(公告)号：US20210066378A1

公开(公告)日：2021-03-04

申请号：US16724744

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Ying Tsai ,  Cheng-Ta Wu ,  Yeur-Luen Tu

IPC: H01L27/146 ,  H01L23/48 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first through substrate via (TSV) disposed within a semiconductor substrate. The semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the semiconductor substrate. The semiconductor substrate comprises a first doped channel region extending from the front-side surface to the back-side surface. The first TSV is defined at least by the first doped channel region. A conductive contact overlies the back-side surface of the semiconductor substrate and comprises a first conductive layer overlying the first TSV. The first conductive layer comprises a conductive material. An upper conductive layer underlies the conductive contact. An upper surface of the upper conductive layer is aligned with the back-side surface of the semiconductor substrate. The upper conductive layer comprises a silicide of the conductive material.

公开(公告)号：US20200258989A1

公开(公告)日：2020-08-13

申请号：US16861478

申请日：2020-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/311 ,  H01L21/66 ,  H01L21/324 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US20200176306A1

公开(公告)日：2020-06-04

申请号：US16546798

申请日：2019-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Pu-Fang Chen ,  Cheng-Ta Wu ,  Po-Jung Chiang ,  Ru-Liang Lee ,  Victor Y. Lu ,  Yen-Hsiu Chen ,  Yeur-Luen Tu ,  Yu-Lung Yeh ,  Shi-Chieh Lin

IPC: H01L21/762 ,  H01L21/02

Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

公开(公告)号：US20190157138A1

公开(公告)日：2019-05-23

申请号：US15904915

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16

Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.

公开(公告)号：US10079257B2

公开(公告)日：2018-09-18

申请号：US13755376

申请日：2013-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsing-Lien Lin ,  Yeur-Luen Tu ,  Cheng-Yuan Tsai ,  Cheng-Ta Wu ,  Chia-Shiung Tsai

IPC: H01L31/0216 ,  H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/14609 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685 ,  H01L31/02168

Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method includes depositing a metal oxide anti-reflection laminate on the first surface of the substrate. The metal oxide anti-reflection laminate includes one or more composite layers of thin metal oxides stacked over the photodiode. Each composite layer includes two or more metal oxide layers: one metal oxide is a high energy band gap metal oxide and another metal oxide is a high refractive index metal oxide.

公开(公告)号：US10062787B2

公开(公告)日：2018-08-28

申请号：US15415790

申请日：2017-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ting Hsiao ,  Cheng-Ta Wu ,  Lun-Kuang Tan ,  Liang-Yu Yen ,  Ting-Chun Wang ,  Tsung-Han Wu ,  Wei-Ming You

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L23/535 ,  H01L29/66 ,  H01L21/3215

CPC classification number: H01L29/7856 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.