公开(公告)号：US20210066164A1

公开(公告)日：2021-03-04

申请号：US16798431

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Jung Wu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Sheng-Tsung Hsiao ,  Jen-Yu Wang

IPC: H01L23/46 ,  H01L23/40 ,  H01L23/498 ,  H01L21/52

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

公开(公告)号：US09893046B2

公开(公告)日：2018-02-13

申请号：US15205238

申请日：2016-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Chun Yang ,  Yi-Li Hsiao ,  Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/30604 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.

公开(公告)号：US20150108206A1

公开(公告)日：2015-04-23

申请号：US14057117

申请日：2013-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Li Hsiao ,  Da-Yuan Shih ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC: B23K3/06 ,  B23K1/20

CPC classification number: B23K3/0638 ,  B23K1/20 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13301 ,  H01L2224/13309 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13318 ,  H01L2224/1332 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K3/3484 ,  H05K2203/041 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01048 ,  H01L2924/014 ,  H01L2924/013

Abstract: Some embodiments of the present disclosure relate to an apparatus and method to form a pattern of solder bumps. A solder paste is applied a plate comprising a pattern of holes, where each hole is partially filled by a piston attached to a movable stage. The remainder of the holes are filled by applying a force to the solder paste with a first solder paste application tool. A second solder paste application tool then removes excess paste from the front surface of the plate. The solder paste is then disposed onto a surface of a substrate by moving the movable stage, which fills a larger portion of each hole with a piston, forces the solder paste out of each hole, and forms pattern of solder paste on the surface of the substrate. The pattern of solder paste is then subjected to additional processing to form a pattern of solder bumps.

Abstract translation: 本公开的一些实施例涉及形成焊料凸块图案的装置和方法。 焊膏被施加包括孔图案的板，其中每个孔由附接到可移动台的活塞部分地填充。 通过用第一焊膏施加工具向焊膏施加力来填补剩余的孔。 然后第二个焊膏应用工具从板的前表面去除多余的糊状物。 然后通过移动填充每个孔的较大部分的可移动台用活塞将焊膏设置在基板的表面上，迫使焊膏从每个孔中出来，并在焊料的表面上形成焊膏图案 基质。 然后对焊膏的图案进行附加处理以形成焊料凸块的图案。

公开(公告)号：US20240038718A1

公开(公告)日：2024-02-01

申请号：US17815088

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Nan Hung ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L23/481 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/0652 ,  H01L24/96 ,  H01L24/97 ,  H01L24/94 ,  H01L21/561

Abstract: A method includes directly bonding a first wafer to a second wafer, wherein the bonding electrically connects a first interconnect structure of the first wafer to a second interconnect structure of the second wafer; directly bonding first semiconductor devices to the second wafer, wherein the bonding electrically connects the first semiconductor devices to the second interconnect structure; encapsulating the first semiconductor devices with a first encapsulant; and forming solder bumps over the first semiconductor devices.

公开(公告)号：US20230361068A1

公开(公告)日：2023-11-09

申请号：US17813411

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Sey-Ping Sun ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/80 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1437

Abstract: Methods of fusion bonding semiconductor dies in packaged semiconductor devices and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor package includes a first die including a semiconductor substrate and a through via extending through the semiconductor substrate; a second die bonded to the first die, the second die including a bond pad, the bond pad being physically and electrically coupled to the through via by metal-to-metal bonds; and an encapsulating material on the first die and laterally encapsulating the second die.

公开(公告)号：US20230170320A1

公开(公告)日：2023-06-01

申请号：US18153847

申请日：2023-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chih-Hang Tung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2224/08145 ,  H01L2224/80895

Abstract: A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

公开(公告)号：US11456256B2

公开(公告)日：2022-09-27

申请号：US16885282

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang ,  Wen-Lin Shih

IPC: H01L23/538 ,  H01L23/373 ,  H01L25/065 ,  H01L21/768 ,  H01L21/50

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

公开(公告)号：US11387164B2

公开(公告)日：2022-07-12

申请号：US16798431

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Jung Wu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Sheng-Tsung Hsiao ,  Jen-Yu Wang

IPC: H01L23/46 ,  H01L21/52 ,  H01L23/40 ,  H01L23/498 ,  H01L23/473 ,  H01L23/42

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

公开(公告)号：US20210375766A1

公开(公告)日：2021-12-02

申请号：US16885282

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang ,  Wen-Lin Shih

IPC: H01L23/538 ,  H01L23/373 ,  H01L25/065 ,  H01L21/50 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

公开(公告)号：US11101195B2

公开(公告)日：2021-08-24

申请号：US16373915

申请日：2019-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Liang Shao ,  Wen-Lin Shih ,  Su-Chun Yang ,  Chih-Hang Tung ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00

Abstract: A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.