公开(公告)号：US20220029011A1

公开(公告)日：2022-01-27

申请号：US17157330

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US10727064B2

公开(公告)日：2020-07-28

申请号：US16450460

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Chien-Hao Chen ,  Chih-Tang Peng ,  Jei Ming Chen ,  Shu-Yi Wang

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/78

Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.

公开(公告)号：US10707114B2

公开(公告)日：2020-07-07

申请号：US16049520

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun Tsai ,  Bing-Hung Chen ,  Chien-Hsun Wang ,  Cheng-Tung Lin ,  Chih-Tang Peng ,  De-Fang Chen ,  Huan-Just Lin ,  Li-Ting Wang ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/311 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/41

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

公开(公告)号：US20190341294A1

公开(公告)日：2019-11-07

申请号：US16517934

申请日：2019-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Shiou Huang ,  Bang-Tai Tang ,  Chih-Tang Peng ,  Tai-Chun Huang ,  Yen-Chun Huang

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/8234

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).

公开(公告)号：US20190006228A1

公开(公告)日：2019-01-03

申请号：US15876583

申请日：2018-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Shiou Huang ,  Bang-Tai Tang ,  Chih-Tang Peng ,  Tai-Chun Huang ,  Yen-Chun Huang

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).

公开(公告)号：US20240387237A1

公开(公告)日：2024-11-21

申请号：US18786479

申请日：2024-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chih-Tang Peng ,  Chi On Chui

IPC: H01L21/762 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device a method of forming the same are provided. The semiconductor device includes a substrate, a first isolation structure and a second isolation structure over the substrate, a semiconductor fin over the substrate and between the first isolation structure and the second isolation structure, and a third isolation structure extending through the semiconductor fin and between the first isolation structure and the second isolation structure. A top surface of the semiconductor fin is above a top surface of the first isolation structure and a top surface of the second isolation structure. The third isolation structure includes a first dielectric material and a second dielectric material over the first dielectric material. An interface between the first dielectric material and the second dielectric material is below the top surface of the first isolation structure and the top surface of the second isolation structure.

公开(公告)号：US11791154B2

公开(公告)日：2023-10-17

申请号：US17813968

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Je-Ming Kuo ,  Yen-Chun Huang ,  Chih-Tang Peng ,  Tien-I Bao

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/8234 ,  B05D3/06 ,  B05D7/00 ,  H01L21/768 ,  B05D1/00 ,  B05D1/38 ,  G03F7/16

CPC classification number: H01L21/02282 ,  B05D3/067 ,  B05D7/546 ,  H01L21/0223 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/02348 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/0649 ,  B05D1/005 ,  B05D1/38 ,  G03F7/162 ,  H01L21/02255 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832

Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.

公开(公告)号：US20220367180A1

公开(公告)日：2022-11-17

申请号：US17813968

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Je-Ming Kuo ,  Yen-Chun Huang ,  Chih-Tang Peng ,  Tien-I Bao

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/8234

Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.

公开(公告)号：US11387138B2

公开(公告)日：2022-07-12

申请号：US16362965

申请日：2019-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Tang Peng ,  Shuen-Shin Liang ,  Keng-Chu Lin ,  Teng-Chun Tsai

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02

Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

公开(公告)号：US10468409B2

公开(公告)日：2019-11-05

申请号：US15920967

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Lee ,  Jian-Shiou Huang ,  Chih-Tang Peng ,  Sung-En Lin

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/108

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure protruding from a semiconductor substrate. The fin structure includes a first portion and an overlying second portion. The first portion is formed of a material that is the same as that of the semiconductor substrate and different from that of the second portion. The semiconductor device structure also includes a liner structure and an isolation feature. The liner structure includes a carbon-doped silicon oxide film covering the semiconductor substrate and the first portion of the first fin structure and a nitrogen-containing film over the carbon-doped silicon oxide film. The isolation feature is over the nitrogen-containing film and surrounded by the liner structure.