公开(公告)号：US20220359745A1

公开(公告)日：2022-11-10

申请号：US17872825

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

公开(公告)号：US20210391184A1

公开(公告)日：2021-12-16

申请号：US16898655

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L21/306 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.

公开(公告)号：US20210376101A1

公开(公告)日：2021-12-02

申请号：US16887219

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Ren Wang ,  Yun-Min Chang ,  Yu-Lien Huang ,  Ching-Feng Fu

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

Abstract: A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.

公开(公告)号：US20210175126A1

公开(公告)日：2021-06-10

申请号：US17181217

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chang-Yun Chang ,  Ching-Feng Fu ,  Peng Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L27/088 ,  H01L23/522 ,  H01L21/768 ,  H01L23/485 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.

公开(公告)号：US10930564B2

公开(公告)日：2021-02-23

申请号：US16536913

申请日：2019-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chang-Yun Chang ,  Ching-Feng Fu ,  Peng Wang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485

Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.

公开(公告)号：US09502533B2

公开(公告)日：2016-11-22

申请号：US14835958

申请日：2015-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

公开(公告)号：US11916147B2

公开(公告)日：2024-02-27

申请号：US17852899

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu ,  Yun-Min Chang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/165 ,  H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76802 ,  H01L21/76877 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/2236 ,  H01L21/266 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66636

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

公开(公告)号：US11888064B2

公开(公告)日：2024-01-30

申请号：US16889028

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823443 ,  H01L21/823821 ,  H01L29/41791 ,  H01L29/4975 ,  H01L29/66795

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

公开(公告)号：US20230352345A1

公开(公告)日：2023-11-02

申请号：US18345188

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chang-Yun Chang ,  Ching-Feng Fu ,  Peng Wang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485 ,  H01L29/06

CPC classification number: H01L21/823475 ,  H01L21/823431 ,  H01L21/76802 ,  H01L29/41791 ,  H01L29/785 ,  H01L23/5226 ,  H01L21/76877 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0649 ,  H01L29/0642 ,  H01L21/823481

Abstract: A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.

公开(公告)号：US11694931B2

公开(公告)日：2023-07-04

申请号：US17181217

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chang-Yun Chang ,  Ching-Feng Fu ,  Peng Wang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485 ,  H01L29/06

CPC classification number: H01L21/823475 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823481

Abstract: A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.