公开(公告)号：US20210375927A1

公开(公告)日：2021-12-02

申请号：US17012848

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11556

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US20210313396A1

公开(公告)日：2021-10-07

申请号：US17346855

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Tsung-Hsien Chang ,  Yu-Shu Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

公开(公告)号：US11063217B2

公开(公告)日：2021-07-13

申请号：US16983928

申请日：2020-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A semiconductor device includes an inter-layer dielectric (ILD) layer, a first metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a second metallization pattern. The first metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer, in which the etch stop layer has a portion extending beyond an edge of the metal-containing compound layer. The memory cell is over the metal-containing compound layer and including a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The second metallization pattern extends through the portion of the etch stop layer to the first metallization pattern.

公开(公告)号：US11030380B2

公开(公告)日：2021-06-08

申请号：US16548253

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin

IPC: G06F30/398 ,  G06F30/327 ,  G06F119/18

Abstract: A synergistic design method for an integrated circuit (IC) is provided. The synergistic design method includes forming a standard cell library and a non-standard cell library, implementing an IC design process from a high-level behavior specification through a gate-level netlist to a physical layout, and verifying the physical layout to fabricate the IC. Each standard cell of the standard cell library performs a Boolean logic operation. Each non-standard cell of the non-standard cell library performs a complex function beyond the Boolean logic operation. A conversion process is executed for translating a circuit function into a Boolean network to generate the gate-level netlist based on the standard cells of the standard cell library corresponding to the circuit function. A direct mapping is executed on the non-standard cell by skipping the conversion process during the IC design process to generate the gate-level netlist.

公开(公告)号：US10971684B2

公开(公告)日：2021-04-06

申请号：US16412810

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Chung-Te Lin ,  Gerben Doornbos ,  Marcus Johannes Henricus van Dal

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

公开(公告)号：US10971682B2

公开(公告)日：2021-04-06

申请号：US16866101

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Sheng-Chih Lai ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02

Abstract: A method for fabricating a memory device is provided. The method includes depositing a resistance switching element layer over a bottom electrode layer; depositing a top electrode layer over the resistance switching element layer; etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack; depositing a first spacer layer over the memory stack and; etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack; depositing a second spacer layer over the memory stack and the first spacer; etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer; and depositing an etch stop layer over and in contact with a top of the second spacer, wherein the etch stop layer is spaced apart from the first spacer by a portion of the second spacer.

公开(公告)号：US10733352B2

公开(公告)日：2020-08-04

申请号：US15965358

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung Chen ,  Chung-Te Lin ,  Fong-Yuan Chang ,  Ho Che Yu ,  Li-Chun Tien

IPC: G06F17/50 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/394

Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.

公开(公告)号：US10559558B2

公开(公告)日：2020-02-11

申请号：US15966507

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Sheng-Hsiung Chen ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Jung-Chan Yang ,  Lee-Chung Lu ,  Po-Hsiang Huang ,  Chun-Chen Chen

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a wire cut between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the wire cut separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US10269784B2

公开(公告)日：2019-04-23

申请号：US15201200

申请日：2016-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

公开(公告)号：US20190035811A1

公开(公告)日：2019-01-31

申请号：US16045058

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chun-Chen Chen ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Chung-Te Lin ,  Jerry Chang Jui Kao ,  Sheng-Hsiung Chen ,  Chin-Chou Liu

IPC: H01L27/118 ,  H01L27/02 ,  G06F17/50

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.