公开(公告)号：US12171091B2

公开(公告)日：2024-12-17

申请号：US18446593

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US11923405B2

公开(公告)日：2024-03-05

申请号：US17750729

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hung-Chao Kao ,  Yuan-Yang Hsiao ,  Tsung-Chieh Hsiao ,  Hsiang-Ku Shen ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L49/02 ,  H10B61/00

CPC classification number: H01L28/60 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76805 ,  H10B61/10

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

公开(公告)号：US11688759B2

公开(公告)日：2023-06-27

申请号：US17305276

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Ming-Hong Kao ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L28/60

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a bottom electrode, a first oxide layer adjacent the bottom electrode, and a first high-k dielectric layer over the bottom electrode and the first oxide layer. A middle electrode is over the first high-k dielectric layer and a second oxide layer is adjacent the middle electrode. A second high-k dielectric layer may be over the middle electrode and the second oxide layer, a top electrode may be over the second high-k dielectric layer.

公开(公告)号：US20220328440A1

公开(公告)日：2022-10-13

申请号：US17854840

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/48

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

公开(公告)号：US11380639B2

公开(公告)日：2022-07-05

申请号：US17114112

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/48

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

公开(公告)号：US11189538B2

公开(公告)日：2021-11-30

申请号：US16411529

申请日：2019-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Mao-Nan Wang ,  Kuo-Chin Chang ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/522 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.

公开(公告)号：US20210098399A1

公开(公告)日：2021-04-01

申请号：US16936910

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Chih-Sheng Li ,  Chih-Hung Lu ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/02

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.

公开(公告)号：US10734283B2

公开(公告)日：2020-08-04

申请号：US16049305

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Chi Chen ,  Hsiang-Ku Shen ,  Jeng-Ya David Yeh

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

公开(公告)号：US20200168574A1

公开(公告)日：2020-05-28

申请号：US16392024

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L23/522

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

公开(公告)号：US11855022B2

公开(公告)日：2023-12-26

申请号：US17854840

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/06 ,  H01L21/4814 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/5223 ,  H01L24/02 ,  H01L24/05 ,  H01L24/07 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05015 ,  H01L2224/05555 ,  H01L2224/0603 ,  H01L2224/16227

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.