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    Field-effect transistor and method of manufacturing the same
    24.
    发明授权
    Field-effect transistor and method of manufacturing the same 有权

    公开(公告)号：US11164948B2

    公开(公告)日：2021-11-02

    申请号：US16805841

    申请日：2020-03-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsai-Jung Ho ,  Jr-Hung Li ,  Tze-Liang Lee ,  Pei-Yu Chou ,  Chi-Ta Lee

    IPC: H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

    Abstract: A field effect transistor includes a semiconductor substrate, source and drain regions, lower source and drain contacts, a metal gate, a first interlayer dielectric layer, a capping layer, and an etch stop layer. The source and drain regions are disposed on the semiconductor substrate. The lower source and drain contacts are disposed on the source and drain regions. The metal gate is disposed in between the lower source and drain contacts. The first interlayer dielectric layer encircles the metal gate and the lower source and drain contacts. The capping layer is disposed on the metal gate. The etch stop layer extends on the first interlayer dielectric layer. An etching selectivity for the etch stop layer over the capping layer is greater than 10.

    FORMING ISOLATION REGIONS FOR SEPARATING FINS AND GATE STACKS
    25.
    发明申请
    FORMING ISOLATION REGIONS FOR SEPARATING FINS AND GATE STACKS 有权

    公开(公告)号：US20210335670A1

    公开(公告)日：2021-10-28

    申请号：US16933386

    申请日：2020-07-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Ting Ko ,  Tai-Chun Huang ,  Jr-Hung Li ,  Tze-Liang Lee ,  Chi On Chui

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

    Semiconductor Device and Method
    26.
    发明申请
    Semiconductor Device and Method 有权

    公开(公告)号：US20210183696A1

    公开(公告)日：2021-06-17

    申请号：US17169989

    申请日：2021-02-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Han Chen ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chung-Ting Ko ,  Jr-Hung Li ,  Chi On Chui

    IPC: H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417

    Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.

    Low-k gate spacer and formation thereof
    27.
    发明授权
    Low-k gate spacer and formation thereof 有权

    公开(公告)号：US10854521B2

    公开(公告)日：2020-12-01

    申请号：US16674443

    申请日：2019-11-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

    Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

    Isolation Features and Methods of Fabricating the Same
    29.
    发明申请
    Isolation Features and Methods of Fabricating the Same 审中-公开

    公开(公告)号：US20190157387A1

    公开(公告)日：2019-05-23

    申请号：US15905882

    申请日：2018-02-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： I-Wen Wu ,  Fu-Kai Yang ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Jr-Hung Li ,  Bo-Cyuan Lu

    IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105

    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

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