公开(公告)号：US20190229118A1

公开(公告)日：2019-07-25

申请号：US16368827

申请日：2019-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Ting WANG ,  Teng-Chun TSAI ,  Cheng-Tung LIN ,  De-Fang CHEN ,  Hui-Cheng CHANG

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/265

Abstract: A semiconductor device includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.

公开(公告)号：US20190164758A1

公开(公告)日：2019-05-30

申请号：US16037925

申请日：2018-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Teng-Chun TSAI

IPC: H01L21/033 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/768

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.

公开(公告)号：US20170365707A1

公开(公告)日：2017-12-21

申请号：US15693171

申请日：2017-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gin-Chen HUANG ,  Tzu-Hsiang HSU ,  Chia-Jung HSU ,  Feng-Cheng YANG ,  Teng-Chun TSAI

IPC: H01L29/78 ,  H01L29/12 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L29/12 ,  H01L29/165 ,  H01L29/511 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

公开(公告)号：US20170190017A1

公开(公告)日：2017-07-06

申请号：US14985173

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun TSAI ,  Shen-Nan LEE ,  Yung-Cheng LU ,  Chia-Chiung LO ,  Shwang-Ming JENG ,  Yee-Chia YEO

IPC: B24B37/20

CPC classification number: B24B37/20

Abstract: A polisher includes a wafer carrier, a polishing head, a movement mechanism, and a rotation mechanism. The wafer carrier has a supporting surface. The supporting surface is configured to carry a wafer thereon. The polishing head is present above the wafer carrier. The polishing head has a polishing surface. The polishing surface of the polishing head is smaller than the supporting surface of the wafer carrier. The movement mechanism is configured to move the polishing head relative to the wafer carrier. The rotation mechanism is configured to rotate the polishing head relative to the wafer carrier.

公开(公告)号：US20220362906A1

公开(公告)日：2022-11-17

申请号：US17866538

申请日：2022-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan LEE ,  Te-Chien HOU ,  Teng-Chun TSAI ,  Chung-Wei HSU ,  Chen-Hao WU

IPC: B24B53/017 ,  B24B49/12 ,  B24B37/32 ,  B24B49/00

Abstract: A method includes measuring a first thickness at a first location of the polishing pad and a second thickness at a second location of the polishing pad; obtaining a first reference thickness at the first location of the polishing pad, wherein the first reference thickness is an average thickness of multiple thicknesses at the first location; obtaining a second reference thickness at the second location of the polishing pad, wherein the second reference thickness is an average thickness of multiple thicknesses at the second location; calculating a first thickness difference; calculating a second thickness difference; modifying a conditioning parameter value at the first location of the polishing pad; and sweeping a conditioner across a surface of the polishing pad; and applying a downforce or a sweeping speed to the conditioner that urges the conditioner against the first location of the polishing pad according to the modified conditioning parameter value.

公开(公告)号：US20210287904A1

公开(公告)日：2021-09-16

申请号：US17333639

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Ting-Ting CHEN ,  Teng-Chun TSAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3205

Abstract: A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

公开(公告)号：US20200090983A1

公开(公告)日：2020-03-19

申请号：US16129899

申请日：2018-09-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan LEE ,  Teng-Chun TSAI ,  Chen-Hao WU ,  Chu-An LEE ,  Chun-Hung LIAO ,  Tsung-Ling TSAI

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer; removing a portion of the dielectric layer to form an opening exposing a portion of the conductive layer; filling a ruthenium-containing material in the opening and in contact with the dielectric layer; and polishing the ruthenium-containing material using a slurry including an abrasive and an oxidizer selected from the group consisting of hydrogen peroxide (H2O2), potassium periodate (KIO4), potassium iodate (KIO3), potassium permanganate (KMnO4), iron(III) nitrate (FeNO3) and a combination thereof.

公开(公告)号：US20190160628A1

公开(公告)日：2019-05-30

申请号：US16141680

申请日：2018-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan LEE ,  Te-Chien HOU ,  Teng-Chun TSAI ,  Chung-Wei HSU ,  Chen-Hao WU

IPC: B24B53/017

Abstract: A method is provided and includes: measuring a surface profile of a polishing pad; obtaining a reference profile of the polishing pad; comparing the surface profile of the polishing pad with the reference profile to generate a difference result; determining a conditioning parameter value according to the difference result; and conditioning the polishing pad using the conditioning parameter value.

公开(公告)号：US20190096686A1

公开(公告)日：2019-03-28

申请号：US16138632

申请日：2018-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Wei HSU ,  Yu-Chung SU ,  Chen-Hao WU ,  Shen-Nan LEE ,  Tsung-Ling TSAI ,  Teng-Chun TSAI

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/306

Abstract: A method includes forming a spin-on carbon (SOC) layer over a target structure; chemically treating an upper portion of the SOC layer; forming a sacrificial layer over the SOC layer; performing a chemical mechanical polish (CMP) process on the sacrificial layer until reaching the SOC layer, wherein the chemically treated upper portion of the SOC layer has a higher resistance to the CMP process than that of the sacrificial layer; forming a patterned photoresist layer over the SOC layer after the CMP process; and etching the target structure using the patterned photoresist layer as a mask.

公开(公告)号：US20160322477A1

公开(公告)日：2016-11-03

申请号：US15208393

申请日：2016-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gin-Chen HUANG ,  Tzu-Hsiang HSU ,  Chia-Jung HSU ,  Feng-Cheng YANG ,  Teng-Chun TSAI

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L29/12 ,  H01L29/165 ,  H01L29/511 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

Abstract translation: 半导体器件包括用于第一鳍式场效应晶体管（FET）的第一鳍结构。 第一鳍结构包括从基板突出的第一基底层，设置在第一基底层上的第一中间层和设置在第一中间层上的第一沟道层。 第一翅片结构还包括由防止下层氧化的材料制成的第一保护层。 第一沟道层由SiGe制成，第一中间层包括设置在第一基极层上的第一半导体（例如，SiGe）层和设置在第一半导体层上的第二半导体层（例如Si）。 第一保护层覆盖第一基底层的侧壁，第一半导体层的侧壁和第二半导体层的侧壁。