公开(公告)号：US12255205B2

公开(公告)日：2025-03-18

申请号：US17826845

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Ping Wang ,  Tai-Chun Huang ,  Yung-Cheng Lu ,  Ting-Gang Chen ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H10B99/00

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

公开(公告)号：US20240347623A1

公开(公告)日：2024-10-17

申请号：US18753240

申请日：2024-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Tai-Chun Huang ,  Ming-Chang Wen ,  Shu-Yuan Ku ,  Fu-Kai Yang ,  Tze-Liang Lee ,  Yung-Cheng Lu ,  Yi-Ting Fu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

公开(公告)号：US12087775B2

公开(公告)日：2024-09-10

申请号：US17464369

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chi On Chui ,  Chieh-Ping Wang

IPC: H01L27/00 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02326 ,  H01L21/0259 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.

公开(公告)号：US12068162B2

公开(公告)日：2024-08-20

申请号：US17874670

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31053 ,  H01L21/76227 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

公开(公告)号：US12051735B2

公开(公告)日：2024-07-30

申请号：US17664479

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Tai-Chun Huang ,  Ming-Chang Wen ,  Shu-Yuan Ku ,  Fu-Kai Yang ,  Tze-Liang Lee ,  Yung-Cheng Lu ,  Yi-Ting Fu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

公开(公告)号：US11855185B2

公开(公告)日：2023-12-26

申请号：US17198133

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/66795 ,  H01L21/02178 ,  H01L21/0332 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/66636 ,  H01L29/785

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20230395702A1

公开(公告)日：2023-12-07

申请号：US18364352

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/785 ,  H01L21/02178 ,  H01L21/0332 ,  H01L29/66636

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20250006560A1

公开(公告)日：2025-01-02

申请号：US18828663

申请日：2024-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Ping Wang ,  Ting-Gang Chen ,  Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

公开(公告)号：US20240395907A1

公开(公告)日：2024-11-28

申请号：US18790476

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20230008494A1

公开(公告)日：2023-01-12

申请号：US17464369

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chi On Chui ,  Chieh-Ping Wang

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.