公开(公告)号：US20180012818A1

公开(公告)日：2018-01-11

申请号：US15714099

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/31 ,  H01L29/40 ,  H01L23/00 ,  H01L23/29 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/482 ,  H01L23/532

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US09842761B2

公开(公告)日：2017-12-12

申请号：US15418269

申请日：2017-01-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Chiang ,  Chung-Wei Lin ,  Kuang-Hsin Chen ,  Bor-Zen Tien

IPC: H01L21/82 ,  H01L21/762 ,  H01L21/263 ,  H01L21/266 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/12 ,  H01L21/3115 ,  H01L21/311

CPC classification number: H01L21/76237 ,  H01L21/2636 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and a second fin partially surrounded by a second isolation structure. The second isolation structure has a dopant concentration higher than that of the first isolation structure, and a height difference is between a top surface of the first isolation structure and a top surface of the second isolation structure.

公开(公告)号：US09773716B2

公开(公告)日：2017-09-26

申请号：US15146012

申请日：2016-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/528 ,  H01L29/40 ,  H01L23/29 ,  H01L23/532

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate. The layer includes an opening extending through the layer. A plurality of bar or pillar structures or a tapered region are arranged in a peripheral portion of the opening and laterally surround a central portion of the opening. A metal body extends through the central portion of the opening.

公开(公告)号：US09299658B2

公开(公告)日：2016-03-29

申请号：US14717995

申请日：2015-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L23/525 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/167

CPC classification number: H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with the metal fuse and a fabricating method thereof are provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

Abstract translation: 提供了具有金属熔断器的半导体器件及其制造方法。 金属熔断器连接电子部件（例如，晶体管）和接地的现有虚拟特征。 金属保险丝的保护可以设计为在金属化形成工艺开始时开始。 接地的虚拟特征提供了在线路过程的整个后端期间等离子体对地面充电的路径。 金属保险丝是与二极管相反的过程电平保护，这是电路级保护。 作为工艺级保护，金属保险丝保护随后形成的电路。 此外，除了已经实现的内部虚拟图案之外，芯片中的金属熔断器不需要额外的有源区域。

公开(公告)号：US20150069395A1

公开(公告)日：2015-03-12

申请号：US14024688

申请日：2013-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Wei Yang ,  Yi-Ruei Lin ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/544 ,  H01L29/08 ,  H01L21/66

CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.

Abstract translation: 集成电路包括布置在硅衬底上的多个横向扩散测量结构。 横向扩散测量结构包括p型区域和n型区域，其协作地跨越横向扩散测量结构的相对外边缘之间的预定初始距离。 在发生掺杂剂扩散之后，p型和n型区域在预期位于目标连接位置处的p-n结处相交。

公开(公告)号：US20150001592A1

公开(公告)日：2015-01-01

申请号：US13930161

申请日：2013-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC: H01L23/525 ,  H01L21/306

CPC classification number: H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

Abstract translation: 提供具有金属保险丝的半导体器件。 金属熔断器连接电子部件（例如，晶体管）和接地的现有虚拟特征。 金属保险丝的保护可以设计为在金属化形成工艺开始时开始。 接地的虚拟特征提供了在线路过程的整个后端期间等离子体对地面充电的路径。 金属保险丝是与二极管相反的过程电平保护，这是电路级保护。 作为工艺级保护，金属保险丝保护随后形成的电路。 此外，除了已经实现的内部虚拟图案之外，芯片中的金属熔断器不需要额外的有源区域。

公开(公告)号：US20140374832A1

公开(公告)日：2014-12-25

申请号：US13924731

申请日：2013-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gwo-Chyuan Kuoh ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien ,  Yen-Ming Peng

IPC: H01L29/78 ,  H01L21/768

CPC classification number: H01L29/7843 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/823871 ,  H01L23/00 ,  H01L29/7842 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.

Abstract translation: 本公开内容涉及具有一个或多个后端行（BEOL）选择应力膜的集成芯片，其应用提高BEOL选择应力膜下面的半导体器件的性能的应力，以及相关联的方法 形成。 在一些实施例中，集成芯片具有带有一个或多个具有第一器件类型的半导体器件的半导体衬底。 应力传递元件位于一个或多个半导体器件上方的位置处的后端行堆叠中。 选择应力膜位于应力传递元件上方。 选择应力膜在应力转移元件上引起应力，其中应力具有取决于一个或多个半导体器件的第一器件类型的压缩或拉伸状态。 应力作用在一个或多个半导体器件上以提高它们的性能。

公开(公告)号：US10134626B2

公开(公告)日：2018-11-20

申请号：US15837433

申请日：2017-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Chiang ,  Chung-Wei Lin ,  Kuang-Hsin Chen ,  Bor-Zen Tien

IPC: H01L21/266 ,  H01L21/762 ,  H01L21/263 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/12 ,  H01L21/3115 ,  H01L21/311

Abstract: A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure includes a first doped portion and a second doped portion, and a doped concentration of the second doped portion is different from a doped concentration of the first doped portion. The semiconductor device also includes a first fin partially embedded in the doped isolation structure, and a sidewall surface of the first fin is in direct contact with the first doped portion. The semiconductor device includes a second fin partially embedded in the doped isolation structure, and the doped isolation structure is between the first fin and the second fin, and a sidewall surface of the second fin is in direct contact with the second doped portion.

公开(公告)号：US09349688B2

公开(公告)日：2016-05-24

申请号：US14791555

申请日：2015-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L29/40 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The first layer includes a via opening and a tapered portion proximate to the via opening. The metal layer is formed over the via opening and the tapered portion of the first layer. The metal layer is substantially free from gaps and voids.

公开(公告)号：US09299621B2

公开(公告)日：2016-03-29

申请号：US14024688

申请日：2013-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Wei Yang ,  Yi-Ruei Lin ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/544 ,  H01L21/66 ,  H01L27/088

CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.

Abstract translation: 集成电路包括布置在硅衬底上的多个横向扩散测量结构。 横向扩散测量结构包括p型区域和n型区域，其协作地跨越横向扩散测量结构的相对外边缘之间的预定初始距离。 在发生掺杂剂扩散之后，p型和n型区域在预期位于目标连接位置处的p-n结处相交。