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    MEMORY DEVICE
    21.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20160284387A1

    公开(公告)日：2016-09-29

    申请号：US14670241

    申请日：2015-03-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yen-Huei CHEN ,  Hung-Jen LIAO ,  Chih-Yu LIN ,  Jonathan Tsung-Yung CHANG ,  Wei-Cheng WU

    IPC: G11C7/12 ,  G11C8/08 ,  G11C8/10

    CPC classification number: G11C8/08 ,  G11C11/418

    Abstract: An electronic device is disclosed that includes memory cells, a word line, a selection unit and a self-boosted driver. The memory cells are configured to store data. The word line is coupled to the memory cells. The selection unit is disposed at a first terminal of the word line, and is configured to transmit a selection signal to activate the word line according to one of a read command and a write command. The self-boosted driver is disposed at a second terminal of the word line, and is configured to pull up a voltage level of the word line according to a voltage level of the word line and a control signal.

    Abstract translation: 公开了一种包括存储器单元，字线，选择单元和自增强驱动器的电子设备。 存储单元配置为存储数据。 字线耦合到存储单元。 选择单元设置在字线的第一端子处，并且被配置为根据读取命令和写入命令之一发送选择信号以激活字线。 自升压驱动器设置在字线的第二端子处，并且被配置为根据字线的电压电平和控制信号上拉字线的电压电平。

    MEMORY DEVICE
    22.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20160163380A1

    公开(公告)日：2016-06-09

    申请号：US15016172

    申请日：2016-02-04

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tzu-Kuei LIN ,  Hung-Jen LIAO ,  Yen-Huei CHEN

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/14

    Abstract: A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data, third bit data, and fourth bit data, in which the first bit data and the fourth bit data are configured to be a high logic state, and the second bit data and the third bit data are configured to be a low logic state. The sensing unit is configured to read bit data stored in one of the memory cells according to the first bit data, the second bit data, the third bit data, and the fourth bit data.

    Abstract translation: 一种设备包括存储单元，参考存储单元和感测单元。 参考存储单元被配置为存储第一位数据和第四位数据被配置为高逻辑状态的第一位数据，第二位数据，第三位数据和第四位数据，并且第二位数据 并且第三位数据被配置为低逻辑状态。 感测单元被配置为根据第一位数据，第二位数据，第三位数据和第四位数据读取存储在一个存储器单元中的位数据。

    Variation Tolerant Read Assist Circuit for SRAM
    25.
    发明申请
    Variation Tolerant Read Assist Circuit for SRAM 审中-公开

    公开(公告)号：US20200005858A1

    公开(公告)日：2020-01-02

    申请号：US16376640

    申请日：2019-04-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Hsien-Yu PAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Sahil Preet SINGH

    IPC: G11C11/419 ,  G11C11/412

    Abstract: A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.

    LEVEL SHIFTER CIRCUIT USING BOOSTING CIRCUIT
    26.
    发明申请
    LEVEL SHIFTER CIRCUIT USING BOOSTING CIRCUIT 有权

    公开(公告)号：US20170264276A1

    公开(公告)日：2017-09-14

    申请号：US15065166

    申请日：2016-03-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mahmut Sinangil ,  Hsin-Hsin KO ,  Chiting CHENG ,  Yen-Huei CHEN ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

    IPC: H03K3/356 ,  H03K19/0185

    CPC classification number: H03K3/356113 ,  H03K19/018521

    Abstract: A level shifter circuit is provided that uses a boosting circuit. The boosting circuit is configured to improve the operation of the level shifter circuit when the high voltages of voltage domains across the level shifter circuit are widely separated. A circuit apparatus includes a core level shifter circuit that changes a first voltage of an input signal to a second voltage of an output signal. The circuit apparatus further includes a first boosting circuit that is coupled to the core level shifter circuit and generates a first transient voltage applied to the core level shifter circuit when the input signal transitions from a low value to a high value. The circuit apparatus also includes a second boosting circuit that is coupled to the core level shifter circuit and generates a second transient voltage applied to the core level shifter circuit when the input signal transitions from a high value to a low value.

    MEMORY DEVICE WITH STABLE WRITING AND/OR READING OPERATION
    29.
    发明申请
    MEMORY DEVICE WITH STABLE WRITING AND/OR READING OPERATION 有权
    具有稳定写入和/或读取操作的存储器件

    公开(公告)号：US20160322098A1

    公开(公告)日：2016-11-03

    申请号：US14700135

    申请日：2015-04-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Mohammed HASAN TAUFIQUE ,  Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Yen-Huei CHEN

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C7/22 ,  G11C11/412

    Abstract: A memory device includes a first inverter, a second inverter cross-coupled with the first inverter, an accessing unit, and a switching unit. The accessing unit is configured to discharge an output of the first inverter and charge an output of the second inverter according to signals provided by a first word line and a second word line. The switching unit is configured to disconnect a power from the first inverter and the second inverter according to a signal provided by the first word line.

    Abstract translation: 存储器件包括第一反相器，与第一反相器交叉耦合的第二反相器，存取单元和切换单元。 访问单元被配置为对第一反相器的输出进行放电，并根据由第一字线和第二字线提供的信号对第二反相器的输出进行充电。 开关单元被配置为根据由第一字线提供的信号来断开来自第一逆变器和第二逆变器的电力。

    MEMORY DEVICE
    30.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20160093366A1

    公开(公告)日：2016-03-31

    申请号：US14501623

    申请日：2014-09-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tzu-Kuei LIN ,  Hung-Jen LIAO ,  Yen-Huei CHEN

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/14

    Abstract: An electronic device is disclosed that includes n memory cells, a replica memory array, and a sensing unit. Each of the n memory cells stores bit data, in which n is a positive integer. The replica memory array includes a first reference memory cell having a high logic state, a second reference memory cell having a low logic state, n−1 first pseudo reference memory cells having the low logic state, and n−1 second pseudo reference memory cells having the high logic state. The first reference memory cell and the n−1 first pseudo reference memory cells generate a first signal, and the second reference memory cell and the n−1 second pseudo reference memory cells generate a second signal. The sensing unit determines a logic state of the bit data of one of the n memory cells according to the first signal and the second signal.

    Abstract translation: 公开了一种包括n个存储单元，复制存储器阵列和感测单元的电子设备。 n个存储单元中的每一个存储位数据，其中n是正整数。 复制存储器阵列包括具有高逻辑状态的第一参考存储单元，具有低逻辑状态的第二参考存储单元，具有低逻辑状态的n-1个第一伪参考存储器单元和n-1个第二伪参考存储器单元 具有高逻辑状态。 第一参考存储单元和n-1个第一伪参考存储单元产生第一信号，第二参考存储单元和第n-1个第二伪参考存储单元产生第二信号。 感测单元根据第一信号和第二信号确定n个存储器单元之一的位数据的逻辑状态。

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